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[AVR] Optimize the 16-bit NEGW pseudo instruction
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Authored by benshi001 on Oct 1 2020, 7:43 AM.

Details

Summary

Optimize "NEGW 'Rd+1 : Rd' to

neg Rd+1
neg Rd
sbci Rd+1, 0

Diff Detail

Event Timeline

benshi001 created this revision.Oct 1 2020, 7:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 1 2020, 7:43 AM
benshi001 requested review of this revision.Oct 1 2020, 7:43 AM
benshi001 updated this revision to Diff 295823.Oct 2 2020, 6:59 AM

I think it would be a good idea to add assembly level tests in llvm/test/CodeGen/AVR/neg.ll (see for example llvm/test/CodeGen/AVR/add.ll).

llvm/lib/Target/AVR/AVRInstrInfo.td
747

Is this correct? I only see one neg while both avr-gcc (https://godbolt.org/z/hETcE9) and the code in AVRExpandPseudoInsts.cpp seem to suggest two neg instructions are needed.

benshi001 added inline comments.
llvm/lib/Target/AVR/AVRInstrInfo.td
747

This is a previous typo, thanks. Already fixed.

benshi001 marked an inline comment as done.Oct 31 2020, 10:18 PM

I think it would be a good idea to add assembly level tests in llvm/test/CodeGen/AVR/neg.ll (see for example llvm/test/CodeGen/AVR/add.ll).

The asm level tests are added in llvm/test/CodeGen/AVR/neg.ll, thanks.

aykevl added inline comments.Nov 3 2020, 5:55 PM
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
442

I do not think this is true: the C flag (part of SREG) is used in sbci.

benshi001 updated this revision to Diff 302741.Nov 3 2020, 9:45 PM
benshi001 marked an inline comment as done.
benshi001 added inline comments.
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
442

Fixed. Thanks.

dylanmckay accepted this revision.Nov 16 2020, 10:37 PM

Looks good to me, thanks for the patch!

This revision is now accepted and ready to land.Nov 16 2020, 10:37 PM
This revision was automatically updated to reflect the committed changes.
benshi001 marked an inline comment as done.