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Differential D88624

[GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs
ClosedPublic

Authored by paquette on Sep 30 2020, 5:17 PM.

Details

Reviewers
aemerson
Commits
rG5402d11b1d88: [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs
Summary

Similar to the FP case in AArch64TargetLowering::LowerBR_CC.

Instead of emitting the csets + a tbnz, just emit a compare + bcc (or two bccs, depending on the condition code)

This improves cases like this: https://godbolt.org/z/v8hebx

This is a 0.1% geomean code size improvement for CTMark at -O3.

Diff Detail

Event Timeline

paquette created this revision.Sep 30 2020, 5:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 30 2020, 5:17 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald Transcript
paquette requested review of this revision.Sep 30 2020, 5:17 PM
aemerson added inline comments.Sep 30 2020, 5:31 PM
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
1327

What else could the opcode be?

paquette added inline comments.Sep 30 2020, 5:33 PM
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
1327

Looks like SDAG has handling for overflow ops, so I guess one of those?

aemerson accepted this revision.Oct 1 2020, 1:08 PM

LGTM.

This revision is now accepted and ready to land.Oct 1 2020, 1:08 PM
Closed by commit rG5402d11b1d88: [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs (authored by paquette). · Explain WhyOct 1 2020, 3:34 PM
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG5402d11b1d88: [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
24 lines
test/
CodeGen/
AArch64/
GlobalISel/
555 lines

Diff 295438

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Show First 20 Lines • Show All 1,316 Lines • ▼ Show 20 Lines
bool AArch64InstructionSelector::selectCompareBranch( bool AArch64InstructionSelector::selectCompareBranch(
MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const { MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
const Register CondReg = I.getOperand(0).getReg(); const Register CondReg = I.getOperand(0).getReg();
MachineBasicBlock *DestMBB = I.getOperand(1).getMBB(); MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
MachineInstr *CCMI = MRI.getVRegDef(CondReg); MachineInstr *CCMI = MRI.getVRegDef(CondReg);
if (CCMI->getOpcode() == TargetOpcode::G_TRUNC) if (CCMI->getOpcode() == TargetOpcode::G_TRUNC)
CCMI = MRI.getVRegDef(CCMI->getOperand(1).getReg()); CCMI = MRI.getVRegDef(CCMI->getOperand(1).getReg());
if (CCMI->getOpcode() != TargetOpcode::G_ICMP)
unsigned CCMIOpc = CCMI->getOpcode();
if (CCMIOpc != TargetOpcode::G_ICMP && CCMIOpc != TargetOpcode::G_FCMP)
aemersonUnsubmitted
Not Done
ReplyInline Actions

What else could the opcode be?

aemerson: What else could the opcode be?
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

Looks like SDAG has handling for overflow ops, so I guess one of those?

paquette: Looks like SDAG has handling for overflow ops, so I guess one of those?
return false; return false;
MachineIRBuilder MIB(I);
Register LHS = CCMI->getOperand(2).getReg(); Register LHS = CCMI->getOperand(2).getReg();
Register RHS = CCMI->getOperand(3).getReg(); Register RHS = CCMI->getOperand(3).getReg();
auto Pred =
static_cast<CmpInst::Predicate>(CCMI->getOperand(1).getPredicate());
if (CCMIOpc == TargetOpcode::G_FCMP) {
// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
// totally clean. Some of them require two branches to implement.
emitFPCompare(LHS, RHS, MIB);
AArch64CC::CondCode CC1, CC2;
changeFCMPPredToAArch64CC(Pred, CC1, CC2);
MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB);
if (CC2 != AArch64CC::AL)
MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB);
I.eraseFromParent();
return true;
}
auto VRegAndVal = getConstantVRegValWithLookThrough(RHS, MRI); auto VRegAndVal = getConstantVRegValWithLookThrough(RHS, MRI);
MachineIRBuilder MIB(I);
CmpInst::Predicate Pred =
(CmpInst::Predicate)CCMI->getOperand(1).getPredicate();
MachineInstr *LHSMI = getDefIgnoringCopies(LHS, MRI); MachineInstr *LHSMI = getDefIgnoringCopies(LHS, MRI);
// When we can emit a TB(N)Z, prefer that. // When we can emit a TB(N)Z, prefer that.
// //
// Handle non-commutative condition codes first. // Handle non-commutative condition codes first.
// Note that we don't want to do this when we have a G_AND because it can // Note that we don't want to do this when we have a G_AND because it can
// become a tst. The tst will make the test bit in the TB(N)Z redundant. // become a tst. The tst will make the test bit in the TB(N)Z redundant.
if (VRegAndVal && LHSMI->getOpcode() != TargetOpcode::G_AND) { if (VRegAndVal && LHSMI->getOpcode() != TargetOpcode::G_AND) {
▲ Show 20 Lines • Show All 4,629 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that we don't have to emit a CSINC when emitting a G_FCMP being used by
# a G_BRCOND.
#
# Condition codes which require more than one instruction should have two Bccs.
...
---
name: oeq
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: oeq
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(oeq), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ogt
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ogt
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 12, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ogt), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: oge
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: oge
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 10, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(oge), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: olt
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: olt
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 4, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(olt), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ole
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ole
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 9, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ole), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: one
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: one
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 4, %bb.2, implicit $nzcv
; CHECK: Bcc 12, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(one), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ord
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ord
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 7, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ord), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: uno
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: uno
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 6, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(uno), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ueq
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ueq
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: Bcc 6, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ueq), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ugt
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ugt
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 8, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ugt), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: uge
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: uge
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 5, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(uge), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ult
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ult
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ult), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: ule
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: ule
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 13, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(ule), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1
...
---
name: une
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: une
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $s0, $s1, $w0, $w1
; CHECK: %cmp_lhs:fpr32 = COPY $s0
; CHECK: %cmp_rhs:fpr32 = COPY $s1
; CHECK: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK: Bcc 1, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1:
; CHECK: $s0 = COPY %cmp_lhs
; CHECK: RET_ReallyLR implicit $s0
; CHECK: bb.2:
; CHECK: $s1 = COPY %cmp_rhs
; CHECK: RET_ReallyLR implicit $s1
bb.0:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $s0, $s1, $w0, $w1
%cmp_lhs:fpr(s32) = COPY $s0
%cmp_rhs:fpr(s32) = COPY $s1
%fcmp:gpr(s32) = G_FCMP floatpred(une), %cmp_lhs(s32), %cmp_rhs
%trunc:gpr(s1) = G_TRUNC %fcmp(s32)
G_BRCOND %trunc(s1), %bb.2
G_BR %bb.1
bb.1:
$s0 = COPY %cmp_lhs
RET_ReallyLR implicit $s0
bb.2:
$s1 = COPY %cmp_rhs
RET_ReallyLR implicit $s1