[AArch64] Fix return type of Neon scalar comparison intrinsics

[DavidSpickett]

Summary

The following should have unsigned return types
but were signed:
vceqd_s64 vceqzd_s64 vcged_s64 vcgezd_s64
vcgtd_s64 vcgtzd_s64 vcled_s64 vclezd_s64
vcltd_s64 vcltzd_s64 vtstd_s64

See https://developer.arm.com/documentation/ihi0073/latest

[DavidSpickett]

Links instead of searching the document:
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vceqd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vceqzd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcged_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcgezd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcgtd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcgtzd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcled_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vclezd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcltd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcltzd_s64
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vtstd_s64

There should be one more set of fixes like this, then I'll get a proper types test added. (at least for base Neon)

[efriedma]

LGTM

clang/include/clang/Basic/arm_neon.td

 def SCALAR_FRECPX : IInst<"vrecpx", "11", "SfSd">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Scalar Floating-point Reciprocal Square Root Estimate
 def SCALAR_FRSQRTE : IInst<"vrsqrte", "11", "SfSd">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Scalar Integer Comparison
-def SCALAR_CMEQ : SInst<"vceq", "111", "SlSUl">;
-def SCALAR_CMEQZ : SInst<"vceqz", "11", "SlSUl">;
-def SCALAR_CMGE : SInst<"vcge", "111", "Sl">;
-def SCALAR_CMGEZ : SInst<"vcgez", "11", "Sl">;
-def SCALAR_CMHS : SInst<"vcge", "111", "SUl">;
-def SCALAR_CMLE : SInst<"vcle", "111", "SlSUl">;
-def SCALAR_CMLEZ : SInst<"vclez", "11", "Sl">;
-def SCALAR_CMLT : SInst<"vclt", "111", "SlSUl">;
-def SCALAR_CMLTZ : SInst<"vcltz", "11", "Sl">;
-def SCALAR_CMGT : SInst<"vcgt", "111", "Sl">;
-def SCALAR_CMGTZ : SInst<"vcgtz", "11", "Sl">;
-def SCALAR_CMHI : SInst<"vcgt", "111", "SUl">;
-def SCALAR_CMTST : SInst<"vtst", "111", "SlSUl">;
+def SCALAR_CMEQ : SInst<"vceq", "(U1)11", "SlSUl">;
+def SCALAR_CMEQZ : SInst<"vceqz", "(U1)1", "SlSUl">;
+def SCALAR_CMGE : SInst<"vcge", "(U1)11", "Sl">;
+def SCALAR_CMGEZ : SInst<"vcgez", "(U1)1", "Sl">;
+def SCALAR_CMHS : SInst<"vcge", "(U1)11", "SUl">;
+def SCALAR_CMLE : SInst<"vcle", "(U1)11", "SlSUl">;
+def SCALAR_CMLEZ : SInst<"vclez", "(U1)1", "Sl">;
+def SCALAR_CMLT : SInst<"vclt", "(U1)11", "SlSUl">;
+def SCALAR_CMLTZ : SInst<"vcltz", "(U1)1", "Sl">;
+def SCALAR_CMGT : SInst<"vcgt", "(U1)11", "Sl">;
+def SCALAR_CMGTZ : SInst<"vcgtz", "(U1)1", "Sl">;
+def SCALAR_CMHI : SInst<"vcgt", "(U1)11", "SUl">;
+def SCALAR_CMTST : SInst<"vtst", "(U1)11", "SlSUl">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // Scalar Floating-point Comparison
 def SCALAR_FCMEQ : IInst<"vceq", "(1U)11", "SfSd">;
 def SCALAR_FCMEQZ : IInst<"vceqz", "(1U)1", "SfSd">;
 def SCALAR_FCMGE : IInst<"vcge", "(1U)11", "SfSd">;
 def SCALAR_FCMGEZ : IInst<"vcgez", "(1U)1", "SfSd">;
 def SCALAR_FCMGT : IInst<"vcgt", "(1U)11", "SfSd">;

clang/test/CodeGen/aarch64-neon-intrinsics.c

 void test_vst1_p64_x4(poly64_t *a, poly64x1x4_t b) {
   vst1_p64_x4(a, b);
 }
 
 // CHECK-LABEL: @test_vceqd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp eq i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vceqd_s64(int64_t a, int64_t b) {
-  return (int64_t)vceqd_s64(a, b);
+uint64_t test_vceqd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vceqd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vceqd_u64(
 // CHECK:   [[TMP0:%.*]] = icmp eq i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
 uint64_t test_vceqd_u64(uint64_t a, uint64_t b) {
   return (int64_t)vceqd_u64(a, b);
 }
 
 // CHECK-LABEL: @test_vceqzd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp eq i64 %a, 0
 // CHECK:   [[VCEQZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQZ_I]]
-int64_t test_vceqzd_s64(int64_t a) {
-  return (int64_t)vceqzd_s64(a);
+uint64_t test_vceqzd_s64(int64_t a) {
+  return (uint64_t)vceqzd_s64(a);
 }
 
 // CHECK-LABEL: @test_vceqzd_u64(
 // CHECK:   [[TMP0:%.*]] = icmp eq i64 %a, 0
 // CHECK:   [[VCEQZD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQZD_I]]
 int64_t test_vceqzd_u64(int64_t a) {
   return (int64_t)vceqzd_u64(a);
 }
 
 // CHECK-LABEL: @test_vcged_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sge i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcged_s64(int64_t a, int64_t b) {
-  return (int64_t)vcged_s64(a, b);
+uint64_t test_vcged_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcged_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcged_u64(
 // CHECK:   [[TMP0:%.*]] = icmp uge i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
 uint64_t test_vcged_u64(uint64_t a, uint64_t b) {
   return (uint64_t)vcged_u64(a, b);
 }
 
 // CHECK-LABEL: @test_vcgezd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sge i64 %a, 0
 // CHECK:   [[VCGEZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCGEZ_I]]
-int64_t test_vcgezd_s64(int64_t a) {
-  return (int64_t)vcgezd_s64(a);
+uint64_t test_vcgezd_s64(int64_t a) {
+  return (uint64_t)vcgezd_s64(a);
 }
 
 // CHECK-LABEL: @test_vcgtd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sgt i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcgtd_s64(int64_t a, int64_t b) {
-  return (int64_t)vcgtd_s64(a, b);
+uint64_t test_vcgtd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcgtd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcgtd_u64(
 // CHECK:   [[TMP0:%.*]] = icmp ugt i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
 uint64_t test_vcgtd_u64(uint64_t a, uint64_t b) {
   return (uint64_t)vcgtd_u64(a, b);
 }
 
 // CHECK-LABEL: @test_vcgtzd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sgt i64 %a, 0
 // CHECK:   [[VCGTZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCGTZ_I]]
-int64_t test_vcgtzd_s64(int64_t a) {
-  return (int64_t)vcgtzd_s64(a);
+uint64_t test_vcgtzd_s64(int64_t a) {
+  return (uint64_t)vcgtzd_s64(a);
 }
 
 // CHECK-LABEL: @test_vcled_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sle i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcled_s64(int64_t a, int64_t b) {
-  return (int64_t)vcled_s64(a, b);
+uint64_t test_vcled_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcled_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcled_u64(
 // CHECK:   [[TMP0:%.*]] = icmp ule i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
 uint64_t test_vcled_u64(uint64_t a, uint64_t b) {
   return (uint64_t)vcled_u64(a, b);
 }
 
 // CHECK-LABEL: @test_vclezd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp sle i64 %a, 0
 // CHECK:   [[VCLEZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCLEZ_I]]
-int64_t test_vclezd_s64(int64_t a) {
-  return (int64_t)vclezd_s64(a);
+uint64_t test_vclezd_s64(int64_t a) {
+  return (uint64_t)vclezd_s64(a);
 }
 
 // CHECK-LABEL: @test_vcltd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp slt i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
-int64_t test_vcltd_s64(int64_t a, int64_t b) {
-  return (int64_t)vcltd_s64(a, b);
+uint64_t test_vcltd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vcltd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vcltd_u64(
 // CHECK:   [[TMP0:%.*]] = icmp ult i64 %a, %b
 // CHECK:   [[VCEQD_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCEQD_I]]
 uint64_t test_vcltd_u64(uint64_t a, uint64_t b) {
   return (uint64_t)vcltd_u64(a, b);
 }
 
 // CHECK-LABEL: @test_vcltzd_s64(
 // CHECK:   [[TMP0:%.*]] = icmp slt i64 %a, 0
 // CHECK:   [[VCLTZ_I:%.*]] = sext i1 [[TMP0]] to i64
 // CHECK:   ret i64 [[VCLTZ_I]]
-int64_t test_vcltzd_s64(int64_t a) {
-  return (int64_t)vcltzd_s64(a);
+uint64_t test_vcltzd_s64(int64_t a) {
+  return (uint64_t)vcltzd_s64(a);
 }
 
 // CHECK-LABEL: @test_vtstd_s64(
 // CHECK:   [[TMP0:%.*]] = and i64 %a, %b
 // CHECK:   [[TMP1:%.*]] = icmp ne i64 [[TMP0]], 0
 // CHECK:   [[VTSTD_I:%.*]] = sext i1 [[TMP1]] to i64
 // CHECK:   ret i64 [[VTSTD_I]]
-int64_t test_vtstd_s64(int64_t a, int64_t b) {
-  return (int64_t)vtstd_s64(a, b);
+uint64_t test_vtstd_s64(int64_t a, int64_t b) {
+  return (uint64_t)vtstd_s64(a, b);
 }
 
 // CHECK-LABEL: @test_vtstd_u64(
 // CHECK:   [[TMP0:%.*]] = and i64 %a, %b
 // CHECK:   [[TMP1:%.*]] = icmp ne i64 [[TMP0]], 0
 // CHECK:   [[VTSTD_I:%.*]] = sext i1 [[TMP1]] to i64
 // CHECK:   ret i64 [[VTSTD_I]]
 uint64_t test_vtstd_u64(uint64_t a, uint64_t b) {