AMDGPU: Don't add frame register to frame pseudos

[arsenm]

Summary

We no longer treat the frame register like a function argument, so the
problem this avoided is no longer relevant.

[arsenm]

6daddc213fe56dccf1e88de61065c7fee09deccf

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPU::SI_BR_UNDEF: {
     Br->getOperand(1).setIsUndef(true); // read undef SCC
     MI.eraseFromParent();
     return BB;
   }
   case AMDGPU::ADJCALLSTACKUP:
   case AMDGPU::ADJCALLSTACKDOWN: {
     const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
     MachineInstrBuilder MIB(*MF, &MI);
-
-    // Add an implicit use of the frame offset reg to prevent the restore copy
-    // inserted after the call from being reorderd after stack operations in the
-    // the caller's frame.
     MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
-        .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
-        .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
+      .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
     return BB;
   }
   case AMDGPU::SI_CALL_ISEL: {
     const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
     const DebugLoc &DL = MI.getDebugLoc();
 
     unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);