[AArch64][GlobalISel] Select all-zero G_BUILD_VECTOR into a zero mov.

[aemerson]

Summary

Unfortunately the leaf SDAG patterns aren't supported yet so we need to do this manually, but it's not a significant amount of code anyway.

[aemerson]

ping

[paquette]

LGTM

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::selectInsertElt(
 
   I.eraseFromParent();
   return true;
 }
 
 bool AArch64InstructionSelector::tryOptConstantBuildVec(
     MachineInstr &I, LLT DstTy, MachineRegisterInfo &MRI) const {
   assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
-  assert(DstTy.getSizeInBits() <= 128 && "Unexpected build_vec type!");
-  if (DstTy.getSizeInBits() < 32)
+  unsigned DstSize = DstTy.getSizeInBits();
+  assert(DstSize <= 128 && "Unexpected build_vec type!");
+  if (DstSize < 32)
     return false;
   // Check if we're building a constant vector, in which case we want to
   // generate a constant pool load instead of a vector insert sequence.
   SmallVector<Constant *, 16> Csts;
   for (unsigned Idx = 1; Idx < I.getNumOperands(); ++Idx) {
     // Try to find G_CONSTANT or G_FCONSTANT
     auto *OpMI =
         getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI);
     if (OpMI)
       Csts.emplace_back(
           const_cast<ConstantInt *>(OpMI->getOperand(1).getCImm()));
     else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT,
                                   I.getOperand(Idx).getReg(), MRI)))
       Csts.emplace_back(
           const_cast<ConstantFP *>(OpMI->getOperand(1).getFPImm()));
     else
       return false;
   }
   Constant *CV = ConstantVector::get(Csts);
   MachineIRBuilder MIB(I);
+  if (CV->isNullValue()) {
+    // Until the importer can support immAllZerosV in pattern leaf nodes,
+    // select a zero move manually here.
+    Register DstReg = I.getOperand(0).getReg();
+    if (DstSize == 128) {
+      auto Mov = MIB.buildInstr(AArch64::MOVIv2d_ns, {DstReg}, {}).addImm(0);
+      I.eraseFromParent();
+      return constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI);
+    } else if (DstSize == 64) {
+      auto Mov =
+          MIB.buildInstr(AArch64::MOVIv2d_ns, {&AArch64::FPR128RegClass}, {})
+              .addImm(0);
+      MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
+          .addReg(Mov.getReg(0), 0, AArch64::dsub);
+      I.eraseFromParent();
+      return RBI.constrainGenericRegister(DstReg, AArch64::FPR64RegClass, MRI);
+    }
+  }
   auto *CPLoad = emitLoadFromConstantPool(CV, MIB);
   if (!CPLoad) {
     LLVM_DEBUG(dbgs() << "Could not generate cp load for build_vector");
     return false;
   }
   MIB.buildCopy(I.getOperand(0), CPLoad->getOperand(0));
   RBI.constrainGenericRegister(I.getOperand(0).getReg(),
                                *MRI.getRegClass(CPLoad->getOperand(0).getReg()),

llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---- |
-  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64"
-
-  define <4 x float> @test_f32(float %a, float %b, float %c, float %d) {
-    ret <4 x float> undef
-  }
-
-  define <2 x double> @test_f64(double %a, double %b) {
-    ret <2 x double> undef
-  }
-
-  define <4 x i32> @test_i32(i32 %a, i32 %b, i32 %c, i32 %d) {
-    ret <4 x i32> undef
-  }
-
-  define <2 x i64> @test_i64(i64 %a, i64 %b) {
-    ret <2 x i64> undef
-  }
-
-  define void @test_p0(i64 *%a, i64 *%b) { ret void }
-
-...
 ---
 name:            test_f32
 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 body:             |
-  bb.0 (%ir-block.0):
+  bb.0:
     liveins: $s0, $s1, $s2, $s3
 
     ; CHECK-LABEL: name: test_f32
     ; CHECK: liveins: $s0, $s1, $s2, $s3
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2
     ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s3

 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 body:             |
-  bb.0 (%ir-block.0):
+  bb.0:
     liveins: $d0, $d1, $d2, $d3
 
     ; CHECK-LABEL: name: test_f64
     ; CHECK: liveins: $d0, $d1, $d2, $d3
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub

 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 body:             |
-  bb.0 (%ir-block.0):
+  bb.0:
     liveins: $w0, $w1, $w2, $w3
 
     ; CHECK-LABEL: name: test_i32
     ; CHECK: liveins: $w0, $w1, $w2, $w3
     ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3

 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 body:             |
-  bb.0 (%ir-block.0):
+  bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: test_i64
     ; CHECK: liveins: $x0, $x1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub

 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: true
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 body:             |
-  bb.0 (%ir-block.0):
+  bb.0:
     liveins: $x0, $x1
 
     ; CHECK-LABEL: name: test_p0
     ; CHECK: liveins: $x0, $x1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
     ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]
     ; CHECK: $q0 = COPY [[INSvi64gpr]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:gpr(p0) = COPY $x0
     %1:gpr(p0) = COPY $x1
     %4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)
     $q0 = COPY %4(<2 x p0>)
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            test_v4s32_zero
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: test_v4s32_zero
+    ; CHECK: liveins: $x0
+    ; CHECK: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
+    ; CHECK: $q0 = COPY [[MOVIv2d_ns]]
+    ; CHECK: RET_ReallyLR
+    %0:gpr(p0) = COPY $x0
+    %2:gpr(s32) = G_CONSTANT i32 0
+    %3:fpr(s32) = COPY %2(s32)
+    %4:fpr(s32) = COPY %2(s32)
+    %5:fpr(s32) = COPY %2(s32)
+    %6:fpr(s32) = COPY %2(s32)
+    %1:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32), %5(s32), %6(s32)
+    $q0 = COPY %1(<4 x s32>)
+    RET_ReallyLR
+...
+---
+name:            test_v8s8_zero
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.1:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: test_v8s8_zero
+    ; CHECK: liveins: $x0
+    ; CHECK: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
+    ; CHECK: $d0 = COPY [[COPY]]
+    ; CHECK: RET_ReallyLR
+    %0:gpr(p0) = COPY $x0
+    %2:gpr(s8) = G_CONSTANT i8 0
+    %3:fpr(s8) = COPY %2(s8)
+    %4:fpr(s8) = COPY %2(s8)
+    %5:fpr(s8) = COPY %2(s8)
+    %6:fpr(s8) = COPY %2(s8)
+    %7:fpr(s8) = COPY %2(s8)
+    %8:fpr(s8) = COPY %2(s8)
+    %9:fpr(s8) = COPY %2(s8)
+    %10:fpr(s8) = COPY %2(s8)
+    %1:fpr(<8 x s8>) = G_BUILD_VECTOR %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8), %9(s8), %10(s8)
+    $d0 = COPY %1(<8 x s8>)
+    RET_ReallyLR
+...

llvm/test/CodeGen/AArch64/arm64-vabs.ll

; CHECK: sabdl2.2d
   ret <2 x i64> %res1
 }
 
 define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
 ; CHECK-LABEL: abspattern1:
 ; DAG: abs.2s
 ; DAG-NEXT: ret
 
-; GISEL: neg.2s
-; GISEL: cmge.2s
+; GISEL-DAG: neg.2s
+; GISEL-DAG: cmge.2s
 ; GISEL: bif.8b
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sge <2 x i32> %a, zeroinitializer
         %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
         ret <2 x i32> %abs
 }
 
 define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
; GISEL: bit.16b
         ret <16 x i8> %abs
 }
 
 define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
 ; CHECK-LABEL: abspattern7:
 ; DAG: abs.2d
 ; DAG-NEXT: ret
 
-; GISEL: neg.2d
-; GISEL: cmge.2d
+; GISEL-DAG: neg.2d
+; GISEL-DAG: cmge.2d
 ; GISEL: bit.16b
         %tmp1neg = sub <2 x i64> zeroinitializer, %a
         %b = icmp sle <2 x i64> %a, zeroinitializer
         %abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
         ret <2 x i64> %abs
 }

llvm/test/CodeGen/AArch64/combine-loads.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -O0 -mtriple=aarch64-unknown-unknown | FileCheck %s
 
 define <2 x i64> @z(i64* nocapture nonnull readonly %p) {
 ; CHECK-LABEL: z:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    movi v0.2d, #0000000000000000
 ; CHECK-NEXT:    ldr x9, [x0]
 ; CHECK-NEXT:    ldr x8, [x0, #8]
 ; CHECK-NEXT:    mov v0.d[0], x9
 ; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    ret
   %b = load i64, i64* %p
   %p2 = getelementptr i64, i64* %p, i64 1
   %bb = load i64, i64* %p2
   %r1 = insertelement <2 x i64> zeroinitializer, i64 %b, i32 0
   %r2 = insertelement <2 x i64> %r1, i64 %bb, i32 1
   ret <2 x i64> %r2
 }