[PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

[amyk]

Summary

This patch implements the 128-bit vector divide extended builtins in Clang/LLVM.
These builtins map to the vdivesq and vdiveuq instructions respectively.

[Conanap]

Looks like there's some unit test failures; could you double check?

[Conanap]

LGTM

[amyk]

In D87729#2275667, @Conanap wrote:

Looks like there's some unit test failures; could you double check?

We discussed offline; I've tested this again afterwards and looked into failures. Unit tests failures are not a result of this patch.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "")
 BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "")
 
 // P10 Vector Divide Extended built-ins.
 BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "")
 BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "")
 BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "")
+BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "")
 
 // P10 Vector Multiply High built-ins.
 BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "")
 BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "")
 BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Expand with Mask built-ins.

clang/lib/Headers/altivec.h

 /*===---- altivec.h - Standard header for type generic math ---------------===*\
  *
  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  * See https://llvm.org/LICENSE.txt for license information.
  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  *
 \*===----------------------------------------------------------------------===*/
 
 #ifndef __ALTIVEC_H
 #define __ALTIVEC_H
 
 #ifndef __ALTIVEC__
 #error "AltiVec support not enabled"
 #endif
 
 /* Constants for mapping CR6 bits to predicate result. */
 
 #define __CR6_EQ 0
 #define __CR6_EQ_REV 1
 #define __CR6_LT 2
 #define __CR6_LT_REV 3
#define __VEC_CLASS_FP_NOT_NORMAL (__VEC_CLASS_FP_NAN        | \
                                    __VEC_CLASS_FP_INFINITY)
 
 #define __ATTRS_o_ai __attribute__((__overloadable__, __always_inline__))
 
 #ifdef __POWER9_VECTOR__
 #include <stddef.h>
 #endif
 
 static __inline__ vector signed char __ATTRS_o_ai vec_perm(
     vector signed char __a, vector signed char __b, vector unsigned char __c);
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_perm(vector unsigned char __a, vector unsigned char __b,
          vector unsigned char __c);
 
 static __inline__ vector bool char __ATTRS_o_ai
 vec_perm(vector bool char __a, vector bool char __b, vector unsigned char __c);
 
 static __inline__ vector short __ATTRS_o_ai vec_perm(vector signed short __a,
                                                      vector signed short __b,
                                                      vector unsigned char __c);
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_perm(vector unsigned short __a, vector unsigned short __b,
          vector unsigned char __c);
 
 static __inline__ vector bool short __ATTRS_o_ai vec_perm(
     vector bool short __a, vector bool short __b, vector unsigned char __c);
 
 static __inline__ vector pixel __ATTRS_o_ai vec_perm(vector pixel __a,
                                                      vector pixel __b,
                                                      vector unsigned char __c);

 vec_dive(vector signed long long __a, vector signed long long __b) {
   return __builtin_altivec_vdivesd(__a, __b);
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_dive(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vdiveud(__a, __b);
 }
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_dive(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return __builtin_altivec_vdiveuq(__a, __b);
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_dive(vector signed __int128 __a, vector signed __int128 __b) {
+  return __builtin_altivec_vdivesq(__a, __b);
+}
 #endif
 
 #ifdef __POWER10_VECTOR__
 static __inline__ vector unsigned __int128 __ATTRS_o_ai
 vec_div(vector unsigned __int128 __a, vector unsigned __int128 __b) {
   return __a / __b;
 }
 

clang/test/CodeGen/builtins-ppc-p10vector.c

 }
 
 vector unsigned long long test_vec_dive_ull(void) {
   // CHECK: @llvm.ppc.altivec.vdiveud(<2 x i64> %{{.+}}, <2 x i64> %{{.+}})
   // CHECK-NEXT: ret <2 x i64>
   return vec_dive(vulla, vullb);
 }
 
+vector unsigned __int128 test_vec_dive_u128(void) {
+  // CHECK: @llvm.ppc.altivec.vdiveuq(<1 x i128> %{{.+}}, <1 x i128> %{{.+}})
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_dive(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_dive_s128(void) {
+  // CHECK: @llvm.ppc.altivec.vdivesq(<1 x i128> %{{.+}}, <1 x i128> %{{.+}})
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_dive(vsi128a, vsi128b);
+}
+
 vector signed int test_vec_mulh_si(void) {
   // CHECK: @llvm.ppc.altivec.vmulhsw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}})
   // CHECK-NEXT: ret <4 x i32>
   return vec_mulh(vsia, vsib);
 }
 
 vector unsigned int test_vec_mulh_ui(void) {
   // CHECK: @llvm.ppc.altivec.vmulhuw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}})

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vrldmi :
                             [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
                             [IntrNoMem]>;
 
 // Vector Divide Extended Intrinsics.
 def int_ppc_altivec_vdivesw : PowerPC_Vec_WWW_Intrinsic<"vdivesw">;
 def int_ppc_altivec_vdiveuw : PowerPC_Vec_WWW_Intrinsic<"vdiveuw">;
 def int_ppc_altivec_vdivesd : PowerPC_Vec_DDD_Intrinsic<"vdivesd">;
 def int_ppc_altivec_vdiveud : PowerPC_Vec_DDD_Intrinsic<"vdiveud">;
+def int_ppc_altivec_vdivesq : PowerPC_Vec_QQQ_Intrinsic<"vdivesq">;
+def int_ppc_altivec_vdiveuq : PowerPC_Vec_QQQ_Intrinsic<"vdiveuq">;
 
 // Vector Multiply High Intrinsics.
 def int_ppc_altivec_vmulhsw : PowerPC_Vec_WWW_Intrinsic<"vmulhsw">;
 def int_ppc_altivec_vmulhuw : PowerPC_Vec_WWW_Intrinsic<"vmulhuw">;
 def int_ppc_altivec_vmulhsd : PowerPC_Vec_DDD_Intrinsic<"vmulhsd">;
 def int_ppc_altivec_vmulhud : PowerPC_Vec_DDD_Intrinsic<"vmulhud">;
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
                                  v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
   def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vdivsq $vD, $vA, $vB", IIC_VecGeneral,
                         [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
   def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vdivuq $vD, $vA, $vB", IIC_VecGeneral,
                         [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
   def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                         "vdivesq $vD, $vA, $vB", IIC_VecGeneral, []>;
+                         "vdivesq $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA,
+             v1i128:$vB))]>;
   def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                         "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, []>;
+                         "vdiveuq $vD, $vA, $vB", IIC_VecGeneral,
+                         [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA,
+             v1i128:$vB))]>;
   def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
   def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
   def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
   def VCMPEQUQ_rec : VCMPo <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;
   def VCMPGTSQ_rec : VCMPo <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
   def VCMPGTUQ_rec : VCMPo <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
   def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         "vmodsq $vD, $vA, $vB", IIC_VecGeneral, []>;

llvm/test/CodeGen/PowerPC/p10-vector-divide.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
 
 ; This test case aims to test the vector divide instructions on Power10.
 ; This includes the low order and extended versions of vector divide,
 ; that operate on signed and unsigned words and doublewords.
+; This also includes 128 bit vector divide instructions.
 
 define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vdivud:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vdivud v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %div = udiv <2 x i64> %a, %b

 ; CHECK-LABEL: test_vdiveud:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vdiveud v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %div = tail call <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i64> %div
 }
+
+declare <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128>, <1 x i128>) nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128>, <1 x i128>) nounwind readnone
+
+define <1 x i128> @test_vdivesq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+; CHECK-LABEL: test_vdivesq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vdivesq v2, v2, v3
+; CHECK-NEXT:    blr
+  %tmp = tail call <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128> %x, <1 x i128> %y)
+  ret <1 x i128> %tmp
+}
+
+
+define <1 x i128> @test_vdiveuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+; CHECK-LABEL: test_vdiveuq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vdiveuq v2, v2, v3
+; CHECK-NEXT:    blr
+  %tmp = call <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128> %x, <1 x i128> %y)
+  ret <1 x i128> %tmp
+}