[AMDGPU] Add XDL resource to scheduling model

[rampitec]

LGTM

[foad]

llvm/lib/Target/AMDGPU/SISchedule.td

107–109

As I understand it, from reading comments in MCSchedule.h and TargetSchedule.td, you have to set BufferSize = 0 to model instructions that immediately consume a resource for one or more cycles. It would be useful to do this for some VALU instructions, e.g. some transcendental instructions, that take more than one cycle to issue (on gfx10).

What I don't understand is, for a normal single-cycle issue (on gfx10) SALU or VALU instruction, should we use BufferSize = 0 or 1 ? What practical difference does it make?

[kerbowa]

llvm/lib/Target/AMDGPU/SISchedule.td

107–109

The conclusion I started to come to when working on this was that a BufferSize of 0 makes sense for most resources given our hardware. A BufferSize of 1 is used to model pipelines where a bubble could be introduced if instructions with a data dependency require the same resource. I'm not sure if there is any practical difference for normal VALU or SALU Ops though.

We would also need to model these types of non-nop hazards in the post-RA scheduler. I started working on some infrastructure for that.

[foad]

llvm/lib/Target/AMDGPU/SISchedule.td

107–109

Shouldn't we aim to switch to post-MI-sched instead of improving post-RA-sched?

llvm/lib/Target/AMDGPU/SISchedule.td

def HWVMEM   : ProcResource<1> {
   let BufferSize = 15;  // Taken from S_WAITCNT
 }
 def HWVALU   : ProcResource<1> {
   let BufferSize = 1;
 }
 def HWRC   : ProcResource<1> { // Register destination cache
   let BufferSize = 1;
 }
+def HWXDL   : ProcResource<1> { // MFMA CU
+  let BufferSize = 0;
+}
 
 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
                  int latency> : WriteRes<write, resources> {
   let Latency = latency;
 }
 
 class HWVALUWriteRes<SchedWrite write, int latency> :
   HWWriteRes<write, [HWVALU], latency>;
multiclass SICommonWriteRes {
   def : HWWriteRes<WriteVMEM,    [HWVMEM],   80>;
   def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
 
   def : HWVALUWriteRes<Write32Bit,         1>;
   def : HWVALUWriteRes<Write64Bit,         2>;
   def : HWVALUWriteRes<WriteFloatCvt,      4>;
   def : HWVALUWriteRes<WriteTrans32,       4>;
   def : HWVALUWriteRes<WriteQuarterRate32, 4>;
-  def : HWVALUWriteRes<Write2PassMAI,      2>;
-  def : HWVALUWriteRes<Write8PassMAI,      8>;
-  def : HWVALUWriteRes<Write16PassMAI,    16>;
+
+  let ResourceCycles = [2] in
+  def : HWWriteRes<Write2PassMAI,  [HWXDL], 2>;
+  let ResourceCycles = [8] in
+  def : HWWriteRes<Write8PassMAI,  [HWXDL], 8>;
+  let ResourceCycles = [16] in
+  def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;
 
   def : ReadAdvance<MIVGPRRead, -2>;
   def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32$")>;
 
   // Technically mfma reads can be from 0 to 4 cycles but that does not make
   // sense to model because its register setup is huge. In particular if we
   // properly model read advance as -2 for a vgpr read it will result in a
   // bad scheduling of acc writes before that mfma. To avoid it we would

llvm/test/CodeGen/AMDGPU/schedule-xdl-resource.ll

+; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=machine-scheduler -verify-machineinstrs < %s 2>&1 | FileCheck -enable-var-scope %s
+; REQUIRES: asserts
+
+declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half>, <4 x half>, <32 x float>, i32, i32, i32)
+
+; CHECK: CritRes: {{[0-9]+}} HWXDL
+; CHECK: Picking: Cand SU([[nid:[0-9]+]]) RES-DEMAND
+; CHECK: Scheduling SU([[nid]]) {{.*}} V_MFMA_F32_32X32X4F16
+define amdgpu_kernel void @schedule-xdl-resource(<32 x float> addrspace(1)* %in, <32 x float> addrspace(1)* %out, <4 x half> addrspace(3)* %lds, i32 %stride) #0 {
+  %in_ptr.1 = getelementptr <32 x float>, <32 x float> addrspace(1)* %in, i32 %stride
+  %in_ptr.2 = getelementptr <32 x float>, <32 x float> addrspace(1)* %in_ptr.1, i32 %stride
+  %in_ptr.3 = getelementptr <32 x float>, <32 x float> addrspace(1)* %in_ptr.2, i32 %stride
+  %in.load.1 = load <32 x float>, <32 x float> addrspace (1)* %in_ptr.1
+  %in.load.2 = load <32 x float>, <32 x float> addrspace (1)* %in_ptr.2
+  %in.load.3 = load <32 x float>, <32 x float> addrspace (1)* %in_ptr.3
+  %lds_ptr.1 = getelementptr <4 x half>, <4 x half> addrspace(3)* %lds, i32 %stride
+  %lds_ptr.2 = getelementptr <4 x half>, <4 x half> addrspace(3)* %lds_ptr.1, i32 %stride
+  %lds_ptr.3 = getelementptr <4 x half>, <4 x half> addrspace(3)* %lds_ptr.2, i32 %stride
+  %lds.load.1 = load <4 x half>, <4 x half> addrspace(3)* %lds_ptr.1
+  %lds.load.2 = load <4 x half>, <4 x half> addrspace(3)* %lds_ptr.2
+  %lds.load.3 = load <4 x half>, <4 x half> addrspace(3)* %lds_ptr.3
+  %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.1, <4 x half> %lds.load.1, <32 x float> %in.load.1, i32 1, i32 1, i32 1)
+  %mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.2, <4 x half> %lds.load.2, <32 x float> %in.load.2, i32 1, i32 1, i32 1)
+  %mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.3, <4 x half> %lds.load.3, <32 x float> %in.load.3, i32 1, i32 1, i32 1)
+  %mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.1, <4 x half> %lds.load.1, <32 x float> %in.load.1, i32 2, i32 2, i32 2)
+  %mai.5 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.2, <4 x half> %lds.load.2, <32 x float> %in.load.2, i32 2, i32 2, i32 2)
+  %mai.6 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.3, <4 x half> %lds.load.3, <32 x float> %in.load.3, i32 2, i32 2, i32 2)
+  %out_ptr.1 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out, i32 %stride
+  %out_ptr.2 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.1, i32 %stride
+  %out_ptr.3 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.2, i32 %stride
+  %out_ptr.4 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.3, i32 %stride
+  %out_ptr.5 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.4, i32 %stride
+  %out_ptr.6 = getelementptr <32 x float>, <32 x float> addrspace(1)* %out_ptr.5, i32 %stride
+  store <32 x float> %mai.1, <32 x float> addrspace(1)* %out_ptr.1
+  store <32 x float> %mai.2, <32 x float> addrspace(1)* %out_ptr.2
+  store <32 x float> %mai.3, <32 x float> addrspace(1)* %out_ptr.3
+  store <32 x float> %mai.4, <32 x float> addrspace(1)* %out_ptr.4
+  store <32 x float> %mai.5, <32 x float> addrspace(1)* %out_ptr.5
+  store <32 x float> %mai.6, <32 x float> addrspace(1)* %out_ptr.6
+
+  ret void
+}
+
+attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }