This is an archive of the discontinued LLVM Phabricator instance.

Differential D86784

[ARM] Skip combining base updates for vld1x NEON intrinsics
ClosedPublic

Authored by SjoerdMeijer on Aug 28 2020, 7:01 AM.

Details

Reviewers
kristof.beyls
efriedma
dmgreen
srhines
Commits
rG5f1cad4d296a: [ARM] Skip combining base updates for vld1x NEON intrinsics
Summary

Skip this for now, to avoid a back-end crash in:

UNREACHABLE executed at /disk/llvm/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp:13412

This should fix PR45824.

Diff Detail

Event Timeline

SjoerdMeijer created this revision.Aug 28 2020, 7:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 28 2020, 7:01 AM
Herald added subscribers: danielkiss, hiraditya. · View Herald Transcript
SjoerdMeijer requested review of this revision.Aug 28 2020, 7:01 AM
dmgreen accepted this revision.Aug 28 2020, 7:12 AM

LGTM.

llvm/test/CodeGen/ARM/pr45824.ll
30

You can possibly simplify these tests a bit. Something like the tests in mve-vld2-post.ll might work, which return the postinc value.

This revision is now accepted and ready to land.Aug 28 2020, 7:12 AM
SjoerdMeijer added inline comments.Aug 28 2020, 12:26 PM
llvm/test/CodeGen/ARM/pr45824.ll
30

Hi Dave, thanks for looking, and you're right that the test can be simplified. I had a quick look, but need more time for this. That's why I will commit this first to unblock other work, and follow up on this to simplify the tests when I am back in the office.

Closed by commit rG5f1cad4d296a: [ARM] Skip combining base updates for vld1x NEON intrinsics (authored by SjoerdMeijer). · Explain WhyAug 28 2020, 12:31 PM
This revision was automatically updated to reflect the committed changes.
SjoerdMeijer added a commit: rG5f1cad4d296a: [ARM] Skip combining base updates for vld1x NEON intrinsics.
SjoerdMeijer added inline comments.Sep 7 2020, 7:21 AM
llvm/test/CodeGen/ARM/pr45824.ll
30

FYI: I've committed a slightly reduced test case in rG288c582fc939. I couldn't really get it down to something smaller than this and still trigger the bug.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
5 lines
test/
CodeGen/
ARM/
100 lines

Diff 288674

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 13,860 Lines • ▼ Show 20 Lines if (isIntrinsic) {
case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
NumVecs = 1; break; NumVecs = 1; break;
case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
NumVecs = 2; break; NumVecs = 2; break;
case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
NumVecs = 3; break; NumVecs = 3; break;
case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
NumVecs = 4; break; NumVecs = 4; break;
case Intrinsic::arm_neon_vld1x2:
case Intrinsic::arm_neon_vld1x3:
case Intrinsic::arm_neon_vld1x4:
case Intrinsic::arm_neon_vld2dup: case Intrinsic::arm_neon_vld2dup:
case Intrinsic::arm_neon_vld3dup: case Intrinsic::arm_neon_vld3dup:
case Intrinsic::arm_neon_vld4dup: case Intrinsic::arm_neon_vld4dup:
// TODO: Support updating VLDxDUP nodes. For now, we just skip // TODO: Support updating VLD1x and VLDxDUP nodes. For now, we just skip
// combining base updates for such intrinsics. // combining base updates for such intrinsics.
continue; continue;
case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
NumVecs = 2; isLaneOp = true; break; NumVecs = 2; isLaneOp = true; break;
case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
NumVecs = 3; isLaneOp = true; break; NumVecs = 3; isLaneOp = true; break;
case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
NumVecs = 4; isLaneOp = true; break; NumVecs = 4; isLaneOp = true; break;
▲ Show 20 Lines • Show All 5,148 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/pr45824.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv7-none-linux-eabi < %s | FileCheck %s
define void @vld1x2([8 x i32] %0) {
; CHECK-LABEL: vld1x2:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: .LBB0_1: @ %.preheader
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: bne .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %.loopexit
; CHECK-NEXT: @ in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r0]
; CHECK-NEXT: b .LBB0_1
%2 = extractvalue [8 x i32] %0, 5
br label %3
3: ; preds = %.loopexit, %1
%4 = getelementptr inbounds i8, i8* undef, i32 undef
br label %.preheader
.preheader: ; preds = %.preheader, %3
%5 = icmp eq i8* %4, undef
br i1 %5, label %.loopexit, label %.preheader
.loopexit: ; preds = %.preheader
%6 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x2.v8i8.p0i8(i8* %4)
%7 = getelementptr inbounds i8, i8* %4, i32 %2
%8 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x2.v8i8.p0i8(i8* %7)
dmgreenUnsubmitted
Not Done
ReplyInline Actions

You can possibly simplify these tests a bit. Something like the tests in mve-vld2-post.ll might work, which return the postinc value.

dmgreen: You can possibly simplify these tests a bit. Something like the tests in mve-vld2-post.ll might…
SjoerdMeijerAuthorUnsubmitted
Done
ReplyInline Actions

Hi Dave, thanks for looking, and you're right that the test can be simplified. I had a quick look, but need more time for this. That's why I will commit this first to unblock other work, and follow up on this to simplify the tests when I am back in the office.

SjoerdMeijer: Hi Dave, thanks for looking, and you're right that the test can be simplified. I had a quick…
SjoerdMeijerAuthorUnsubmitted
Done
ReplyInline Actions

FYI: I've committed a slightly reduced test case in rG288c582fc939. I couldn't really get it down to something smaller than this and still trigger the bug.

SjoerdMeijer: FYI: I've committed a slightly reduced test case in rG288c582fc939. I couldn't really get it…
tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* undef, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 1)
br label %3
}
define void @vld1x3([8 x i32] %0) {
; CHECK-LABEL: vld1x3:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: .LBB1_1: @ %.preheader
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: bne .LBB1_1
; CHECK-NEXT: @ %bb.2: @ %.loopexit
; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r0]
; CHECK-NEXT: b .LBB1_1
%2 = extractvalue [8 x i32] %0, 5
br label %3
3: ; preds = %.loopexit, %1
%4 = getelementptr inbounds i8, i8* undef, i32 undef
br label %.preheader
.preheader: ; preds = %.preheader, %3
%5 = icmp eq i8* %4, undef
br i1 %5, label %.loopexit, label %.preheader
.loopexit: ; preds = %.preheader
%6 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x3.v8i8.p0i8(i8* %4)
%7 = getelementptr inbounds i8, i8* %4, i32 %2
%8 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x3.v8i8.p0i8(i8* %7)
tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* undef, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 1)
br label %3
}
define void @vld1x4([8 x i32] %0) {
; CHECK-LABEL: vld1x4:
; CHECK: @ %bb.0:
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: .LBB2_1: @ %.preheader
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: bne .LBB2_1
; CHECK-NEXT: @ %bb.2: @ %.loopexit
; CHECK-NEXT: @ in Loop: Header=BB2_1 Depth=1
; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r0]
; CHECK-NEXT: b .LBB2_1
%2 = extractvalue [8 x i32] %0, 5
br label %3
3: ; preds = %.loopexit, %1
%4 = getelementptr inbounds i8, i8* undef, i32 undef
br label %.preheader
.preheader: ; preds = %.preheader, %3
%5 = icmp eq i8* %4, undef
br i1 %5, label %.loopexit, label %.preheader
.loopexit: ; preds = %.preheader
%6 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x4.v8i8.p0i8(i8* %4)
%7 = getelementptr inbounds i8, i8* %4, i32 %2
%8 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x4.v8i8.p0i8(i8* %7)
tail call void @llvm.arm.neon.vst3.p0i8.v8i8(i8* undef, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 1)
br label %3
}
declare void @llvm.arm.neon.vst3.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32)
declare { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x2.v8i8.p0i8(i8*)
declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x3.v8i8.p0i8(i8*)
declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x4.v8i8.p0i8(i8*)