[AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR.

[aemerson]

Summary

I'm going to later change the IRTranslator to not remove unnecessary fallthrough G_BRs and leave it down to the target. Implement this in earlySelect() before the tablegen selector can select it.

[paquette]

LGTM

[aemerson]

Actually I'm going to abandon this. I think later CodeGen passes can eliminate these and make better decisions about it.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
   assert(I.getParent() && "Instruction should be in a basic block!");
   assert(I.getParent()->getParent() && "Instruction should be in a function!");
 
   MachineBasicBlock &MBB = *I.getParent();
   MachineFunction &MF = *MBB.getParent();
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   switch (I.getOpcode()) {
+  case TargetOpcode::G_BR:
+    // If the branch jumps to the fallthrough block, don't bother emitting it.
+    if (MBB.isLayoutSuccessor(I.getOperand(0).getMBB())) {
+      I.eraseFromParent();
+      return true;
+    }
+    break;
   case TargetOpcode::G_SHL:
     return earlySelectSHL(I, MRI);
   case TargetOpcode::G_CONSTANT: {
     bool IsZero = false;
     if (I.getOperand(1).isCImm())
       IsZero = I.getOperand(1).getCImm()->getZExtValue() == 0;
     else if (I.getOperand(1).isImm())
       IsZero = I.getOperand(1).getImm() == 0;
if (ProduceNonFlagSettingCondBr && selectCompareBranch(I, MF, MRI))
       return true;
 
     if (ProduceNonFlagSettingCondBr) {
       unsigned BOpc = AArch64::TBNZW;
       // Try to fold a not, i.e. a xor, cond, 1.
       Register XorSrc;
       int64_t Cst;
       if (mi_match(CondReg, MRI,
                    m_GTrunc(m_GXor(m_Reg(XorSrc), m_ICst(Cst)))) &&
           Cst == 1) {
         CondReg = XorSrc;
         BOpc = AArch64::TBZW;
         if (MRI.getType(XorSrc).getSizeInBits() > 32)
           BOpc = AArch64::TBZX;
       }
       auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(BOpc))
                      .addUse(CondReg)

llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir

registers:
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 body:             |
   ; CHECK-LABEL: name: add_imm_s32_gpr_bb
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
   ; CHECK:   $w0 = COPY [[ADDWri]]
   bb.0:
     liveins: $w0, $w1
     successors: %bb.1
 
     %0(s32) = COPY $w0

llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir

body:             |
   ; CHECK:   Bcc 8, %bb.3, implicit $nzcv
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
   ; CHECK:   [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
   ; CHECK:   early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
   ; CHECK:   BR %6
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   B %bb.3
   ; CHECK: bb.3:
   ; CHECK:   RET_ReallyLR
   bb.1:
     %1:gpr(p0) = G_IMPLICIT_DEF
     %5:gpr(s64) = G_ZEXTLOAD %1(p0) :: (load 1)
     %7:gpr(s64) = G_CONSTANT i64 8
     %16:gpr(s32) = G_ICMP intpred(ugt), %5(s64), %7
     %8:gpr(s1) = G_TRUNC %16(s32)

llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir

 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: lr_other_block
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $w0, $x0, $lr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $lr
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
   ; CHECK:   $x0 = COPY [[COPY1]]
   ; CHECK:   RET_ReallyLR implicit $x0
   ; LR should be added as a livein to the entry block.
 
   bb.0:
     ; We should have lr as a livein to bb.0, and a copy from LR.

 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: already_live_in
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $w0, $x0, $lr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $lr
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
   ; CHECK:   $x0 = COPY [[COPY1]]
   ; CHECK:   RET_ReallyLR implicit $x0
   ; We should not have LR listed as a livein twice.
 
   bb.0:
     liveins: $w0, $x0, $lr

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: multi_use
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: $w0, $x0, $lr
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $lr
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   $x0 = COPY [[COPY1]]
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY]]
   ; CHECK:   RET_ReallyLR implicit [[COPY2]]
   bb.0:
     liveins: $w0, $x0, $lr
     %0:gpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
     G_BR %bb.1
   bb.1:
     $x0 = COPY %0
     %1:gpr(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), 0
     RET_ReallyLR implicit %1
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir

registers:
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
 
 body:             |
   ; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
   ; CHECK:   [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]]
   ; CHECK:   $w0 = COPY [[ORNWrr]]
   bb.0:
     liveins: $w0, $w1
     successors: %bb.1
     %1(s32) = G_CONSTANT i32 -1
     G_BR %bb.1
   bb.1:
     %0(s32) = COPY $w0
     %2(s32) = G_XOR %0, %1
     $w0 = COPY %2(s32)
 ...