[GISel] Correct the known bits of G_ANYEXT

[bogner]

Summary

Known bits for G_ANYEXT was incorrectly using KnownBits::zext, causing
us to treat the high bits as zero even though they're (by definition)
unknown.

[arsenm]

LGTM with int

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

528–530

Register

534

Register

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

case TargetOpcode::G_SEXT: {
     // If the sign bit is known to be zero or one, then sext will extend
     // it to the top bits, else it will just zext.
     Known = Known.sext(BitWidth);
     break;
   }
   case TargetOpcode::G_ANYEXT: {
     computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
                          Depth + 1);
-    Known = Known.zext(BitWidth);
+    Known = Known.anyext(BitWidth);
     break;
   }
   case TargetOpcode::G_LOAD: {
     const MachineMemOperand *MMO = *MI.memoperands_begin();
     if (const MDNode *Ranges = MMO->getRanges()) {
       computeKnownBitsFromRangeMetadata(*Ranges, Known);
     }
 

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

TEST_F(AArch64GISelMITest, TestMetadata) {
   EXPECT_TRUE(Res.One.isNullValue());
 
   // We know that the value is in [0, 2). So, we don't know if the first bit
   // is 0 or not. However, we do know that every other bit must be 0.
   APInt Mask(Res.getBitWidth(), 1);
   Mask.flipAllBits();
   EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());
 }
+
+TEST_F(AArch64GISelMITest, TestKnownBitsExt) {
+  StringRef MIRString = "  %c1:_(s16) = G_CONSTANT i16 1\n"
+                        "  %x:_(s16) = G_IMPLICIT_DEF\n"
+                        "  %y:_(s16) = G_AND %x, %c1\n"
+                        "  %anyext:_(s32) = G_ANYEXT %y(s16)\n"
+                        "  %r1:_(s32) = COPY %anyext\n"
+                        "  %zext:_(s32) = G_ZEXT %y(s16)\n"
+                        "  %r2:_(s32) = COPY %zext\n"
+                        "  %sext:_(s32) = G_SEXT %y(s16)\n"
+                        "  %r3:_(s32) = COPY %sext\n";
+  setUp(MIRString);
+  if (!TM)
+    return;
+  Register CopyRegAny = Copies[Copies.size() - 3];
+  Register CopyRegZ = Copies[Copies.size() - 2];
+  Register CopyRegS = Copies[Copies.size() - 1];
+
+  GISelKnownBits Info(*MF);
+  MachineInstr *Copy;
+  Register SrcReg;
+  KnownBits Res;
+
+  Copy = MRI->getVRegDef(CopyRegAny);
+  SrcReg = Copy->getOperand(1).getReg();
+  Res = Info.getKnownBits(SrcReg);
+  EXPECT_EQ((uint64_t)32, Res.getBitWidth());
+  EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
+  EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());
+
+  Copy = MRI->getVRegDef(CopyRegZ);
+  SrcReg = Copy->getOperand(1).getReg();
+  Res = Info.getKnownBits(SrcReg);
+  EXPECT_EQ((uint64_t)32, Res.getBitWidth());
+  EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
+  EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
+
+  Copy = MRI->getVRegDef(CopyRegS);
+  SrcReg = Copy->getOperand(1).getReg();
+  Res = Info.getKnownBits(SrcReg);
+  EXPECT_EQ((uint64_t)32, Res.getBitWidth());
+  EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
+  EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
+}