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[DebugInstrRef][6/9] Pass DBG_INSTR_REFs safely through register allocation

Authored by jmorse on Aug 11 2020, 10:19 AM.



Both FastRegAlloc and LiveDebugVariables/greedy need to cope with DBG_INSTR_REFs. None of them actually need to take any action, other than passing DBG_INSTR_REFs through: variable location information doesn't refer to any registers at this stage.

LiveDebugVariables stashes the instruction information in a tuple, then re-creates it later. This is only necessary as the register allocator doesn't expect to see any debug instructions while it's working. No equivalence classes or interval splitting is required at all!

No changes are needed for the fast register allocator, as it just ignores debug instructions. The test added checks that both of them preserve DBG_INSTR_REFs.

I also expand ScheduleDAGInstrs.cpp to treat DBG_INSTR_REFs as DBG_VALUEs when rescheduling instructions around -- done in this patch as machine-scheduler is part of the register allocation phase, as I understand it. The current movement of DBG_VALUEs around is less than ideal, but it's not a regression to make DBG_INSTR_REFs subject to the same movement.

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jmorse created this revision.Aug 11 2020, 10:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 11 2020, 10:19 AM
aprantl accepted this revision.Aug 11 2020, 11:35 AM
This revision is now accepted and ready to land.Aug 11 2020, 11:35 AM
This revision was landed with ongoing or failed builds.Oct 22 2020, 7:53 AM
This revision was automatically updated to reflect the committed changes.

NB: I said in the test:

The fast register allocator puts some spills in -- these are no-ops as far
as the slot indexes are concerned. It doesn't matter which side of spills
the DBG_INSTR_REF lands on.

And in the mean time, fast-isel has changed where it puts those spills. I updated the relevant CHECK lines to be CHECK-DAGs.