[AArch64][GlobalISel] NFC: Add state class + helper for post-legalizer combiner

[paquette]

Summary

A bit cleaner than having a bunch of static functions.

Also lets us use utility functions from the base CombinerHelper, and keep track of function attributes.

[arsenm]

See also D81899?

llvm/lib/Target/AArch64/AArch64Combine.td

 
 // Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
 // target-specific opcode.
 def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">;
 
 def rev : GICombineRule<
   (defs root:$root, shuffle_matchdata:$matchinfo),
   (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
-         [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
-  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
+         [{ return Helper.matchREV(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
 >;
 
 def zip : GICombineRule<
   (defs root:$root, shuffle_matchdata:$matchinfo),
   (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
-         [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
-  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
+         [{ return Helper.matchZip(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
 >;
 
 def uzp : GICombineRule<
   (defs root:$root, shuffle_matchdata:$matchinfo),
   (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
-         [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
-  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
+         [{ return Helper.matchUZP(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
 >;
 
 def dup: GICombineRule <
   (defs root:$root, shuffle_matchdata:$matchinfo),
   (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
-         [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
-  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
+         [{ return Helper.matchDup(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
 >;
 
 def trn : GICombineRule<
   (defs root:$root, shuffle_matchdata:$matchinfo),
   (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
-         [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
-  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
+         [{ return Helper.matchTRN(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
 >;
 
 def ext: GICombineRule <
   (defs root:$root, shuffle_matchdata:$matchinfo),
   (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
-         [{ return matchEXT(*${root}, MRI, ${matchinfo}); }]),
-  (apply [{ applyEXT(*${root}, ${matchinfo}); }])
+         [{ return Helper.matchEXT(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyEXT(*${root}, ${matchinfo}); }])
 >;
 
 // Combines which replace a G_SHUFFLE_VECTOR with a target-specific pseudo
 // instruction.
 def shuffle_vector_pseudos : GICombineGroup<[dup, rev, ext, zip, uzp, trn]>;
 
 def AArch64PostLegalizerCombinerHelper
     : GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
                        [erase_undef_store, combines_for_extload,
                         sext_trunc_sextload, shuffle_vector_pseudos]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
+  let StateClass = "AArch64PostLegalizerCombinerHelperState";
+  let AdditionalArguments = [
+    GICombinerHelperArg<"AArch64PostLegalizerCombinerHelper &",
+                        "Helper">
+    ];
 }

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

- //=== lib/CodeGen/GlobalISel/AArch64PostLegalizerCombiner.cpp -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This performs post-legalization combines on generic MachineInstrs.
struct ShuffleVectorPseudo {
   Register Dst; ///< Destination register.
   SmallVector<SrcOp, 2> SrcOps; ///< Source registers.
   ShuffleVectorPseudo(unsigned Opc, Register Dst,
                       std::initializer_list<SrcOp> SrcOps)
       : Opc(Opc), Dst(Dst), SrcOps(SrcOps){};
   ShuffleVectorPseudo() {}
 };
 
+class AArch64PostLegalizerCombinerHelper : public CombinerHelper {
+private:
   /// Check if a vector shuffle corresponds to a REV instruction with the
   /// specified blocksize.
-static bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts,
+  bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts,
+                 unsigned BlockSize);
+
+  /// Determines if \p M is a shuffle vector mask for a TRN of \p NumElts.
+  /// Whether or not G_TRN1 or G_TRN2 should be used is stored in \p
+  /// WhichResult.
+  bool isTRNMask(ArrayRef<int> M, unsigned NumElts, unsigned &WhichResult);
+
+  /// Check if a G_EXT instruction can handle a shuffle mask \p M when the
+  /// vector
+  /// sources of the shuffle are different.
+  Optional<std::pair<bool, uint64_t>> getExtMask(ArrayRef<int> M,
+                                                 unsigned NumElts);
+  /// Determines if \p M is a shuffle vector mask for a UZP of \p NumElts.
+  /// Whether or not G_UZP1 or G_UZP2 should be used is stored in \p
+  /// WhichResult.
+  bool isUZPMask(ArrayRef<int> M, unsigned NumElts, unsigned &WhichResult);
+
+  /// \return true if \p M is a zip mask for a shuffle vector of \p NumElts.
+  /// Whether or not G_ZIP1 or G_ZIP2 should be used is stored in \p
+  /// WhichResult.
+  bool isZipMask(ArrayRef<int> M, unsigned NumElts, unsigned &WhichResult);
+
+  /// Helper function for matchDup.
+  bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI,
+                                   ShuffleVectorPseudo &MatchInfo);
+
+  /// Helper function for matchDup.
+  bool matchDupFromBuildVector(int Lane, MachineInstr &MI,
+                               ShuffleVectorPseudo &MatchInfo);
+
+public:
+  AArch64PostLegalizerCombinerHelper(GISelChangeObserver &Observer,
+                                     MachineIRBuilder &B,
+                                     GISelKnownBits *KB = nullptr,
+                                     MachineDominatorTree *MDT = nullptr,
+                                     const LegalizerInfo *LI = nullptr);
+
+  /// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
+  /// a G_REV instruction.
+  ///
+  /// \param [in] MI - The shuffle vector instruction.
+  /// \param [out] MatchInfo - One of G_REV16, G_REV2, or G_REV64 on success.
+  bool matchREV(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+
+  /// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
+  /// a G_TRN1 or G_TRN2 instruction.
+  ///
+  /// \param [in] MI - The shuffle vector instruction.
+  /// \param [out] MatchInfo - Either G_TRN1 or G_TRN2 on success.
+  bool matchTRN(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+
+  /// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
+  /// a G_UZP1 or G_UZP2 instruction.
+  ///
+  /// \param [in] MI - The shuffle vector instruction.
+  /// \param [out] MatchInfo - Either G_UZP1 or G_UZP2 on success.
+  bool matchUZP(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+
+  /// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
+  /// a G_ZIP1 or G_ZIP2 instruction.
+  ///
+  /// \param [in] MI - The shuffle vector instruction.
+  /// \param [out] MatchInfo - Either G_ZIP1 or G_ZIP2 on success.
+  bool matchZip(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+
+  /// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
+  /// a G_DUP instruction.
+  ///
+  /// \param [in] MI - The shuffle vector instruction.
+  /// \param [out] MatchInfo - G_DUP on success.
+  bool matchDup(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+
+  /// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
+  /// a G_EXT instruction.
+  ///
+  /// \param [in] MI - The shuffle vector instruction.
+  /// \param [out] MatchInfo - G_EXT on success.
+  bool matchEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+
+  /// Replace a G_SHUFFLE_VECTOR instruction with a pseudo.
+  /// \p Opc is the opcode to use. \p MI is the G_SHUFFLE_VECTOR.
+  bool applyShuffleVectorPseudo(MachineInstr &MI,
+                                ShuffleVectorPseudo &MatchInfo);
+
+  /// Replace a G_SHUFFLE_VECTOR instruction with G_EXT.
+  /// Special-cased because the constant operand must be emitted as a G_CONSTANT
+  /// for the imported tablegen patterns to work.
+  bool applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo);
+};
+
+AArch64PostLegalizerCombinerHelper::AArch64PostLegalizerCombinerHelper(
+    GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB,
+    MachineDominatorTree *MDT, const LegalizerInfo *LI)
+    : CombinerHelper(Observer, B, KB, MDT, LI) {}
+
+bool AArch64PostLegalizerCombinerHelper::isREVMask(ArrayRef<int> M,
+                                                   unsigned EltSize,
+                                                   unsigned NumElts,
                                                    unsigned BlockSize) {
   assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
          "Only possible block sizes for REV are: 16, 32, 64");
   assert(EltSize != 64 && "EltSize cannot be 64 for REV mask.");
 
   unsigned BlockElts = M[0] + 1;
 
   // If the first shuffle index is UNDEF, be optimistic.
   if (M[0] < 0)
for (unsigned i = 0; i < NumElts; ++i) {
     if (static_cast<unsigned>(M[i]) !=
         (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
       return false;
   }
 
   return true;
 }
 
-/// Determines if \p M is a shuffle vector mask for a TRN of \p NumElts.
-/// Whether or not G_TRN1 or G_TRN2 should be used is stored in \p WhichResult.
-static bool isTRNMask(ArrayRef<int> M, unsigned NumElts,
+bool AArch64PostLegalizerCombinerHelper::isTRNMask(ArrayRef<int> M,
+                                                   unsigned NumElts,
                                                    unsigned &WhichResult) {
   if (NumElts % 2 != 0)
     return false;
   WhichResult = (M[0] == 0 ? 0 : 1);
   for (unsigned i = 0; i < NumElts; i += 2) {
     if ((M[i] >= 0 && static_cast<unsigned>(M[i]) != i + WhichResult) ||
         (M[i + 1] >= 0 &&
          static_cast<unsigned>(M[i + 1]) != i + NumElts + WhichResult))
       return false;
   }
   return true;
 }
 
-/// Check if a G_EXT instruction can handle a shuffle mask \p M when the vector
-/// sources of the shuffle are different.
-static Optional<std::pair<bool, uint64_t>> getExtMask(ArrayRef<int> M,
-                                                      unsigned NumElts) {
+Optional<std::pair<bool, uint64_t>>
+AArch64PostLegalizerCombinerHelper::getExtMask(ArrayRef<int> M,
   // Look for the first non-undef element.
   auto FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; });
   if (FirstRealElt == M.end())
     return None;
 
   // Use APInt to handle overflow when calculating expected element.
   unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
   APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
AArch64PostLegalizerCombinerHelper::getExtMask(ArrayRef<int> M,
   // to reverse two input vectors.
   if (Imm < NumElts)
     ReverseExt = true;
   else
     Imm -= NumElts;
   return std::make_pair(ReverseExt, Imm);
 }
 
-/// Determines if \p M is a shuffle vector mask for a UZP of \p NumElts.
-/// Whether or not G_UZP1 or G_UZP2 should be used is stored in \p WhichResult.
-static bool isUZPMask(ArrayRef<int> M, unsigned NumElts,
+bool AArch64PostLegalizerCombinerHelper::isUZPMask(ArrayRef<int> M,
+                                                   unsigned NumElts,
                                                    unsigned &WhichResult) {
   WhichResult = (M[0] == 0 ? 0 : 1);
   for (unsigned i = 0; i != NumElts; ++i) {
     // Skip undef indices.
     if (M[i] < 0)
       continue;
     if (static_cast<unsigned>(M[i]) != 2 * i + WhichResult)
       return false;
   }
   return true;
 }
 
-/// \return true if \p M is a zip mask for a shuffle vector of \p NumElts.
-/// Whether or not G_ZIP1 or G_ZIP2 should be used is stored in \p WhichResult.
-static bool isZipMask(ArrayRef<int> M, unsigned NumElts,
+bool AArch64PostLegalizerCombinerHelper::isZipMask(ArrayRef<int> M,
+                                                   unsigned NumElts,
                                                    unsigned &WhichResult) {
   if (NumElts % 2 != 0)
     return false;
 
   // 0 means use ZIP1, 1 means use ZIP2.
   WhichResult = (M[0] == 0 ? 0 : 1);
   unsigned Idx = WhichResult * NumElts / 2;
   for (unsigned i = 0; i != NumElts; i += 2) {
-      if ((M[i] >= 0 && static_cast<unsigned>(M[i]) != Idx) ||
-          (M[i + 1] >= 0 && static_cast<unsigned>(M[i + 1]) != Idx + NumElts))
-        return false;
     Idx += 1;
   }
   return true;
 }
 
-/// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with a
-/// G_REV instruction. Returns the appropriate G_REV opcode in \p Opc.
-static bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchREV(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
   ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
   Register Dst = MI.getOperand(0).getReg();
   Register Src = MI.getOperand(1).getReg();
   LLT Ty = MRI.getType(Dst);
   unsigned EltSize = Ty.getScalarSizeInBits();
 
   // Element size for a rev cannot be 64.
bool AArch64PostLegalizerCombinerHelper::matchREV(
   }
 
   // TODO: Produce G_REV32 and G_REV16 once we have proper legalization support.
   // This should be identical to above, but with a constant 32 and constant
   // 16.
   return false;
 }
 
-/// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
-/// a G_TRN1 or G_TRN2 instruction.
-static bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchTRN(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
   unsigned WhichResult;
   ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
   Register Dst = MI.getOperand(0).getReg();
   unsigned NumElts = MRI.getType(Dst).getNumElements();
   if (!isTRNMask(ShuffleMask, NumElts, WhichResult))
     return false;
   unsigned Opc = (WhichResult == 0) ? AArch64::G_TRN1 : AArch64::G_TRN2;
   Register V1 = MI.getOperand(1).getReg();
   Register V2 = MI.getOperand(2).getReg();
   MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
   return true;
 }
 
-/// \return true if a G_SHUFFLE_VECTOR instruction \p MI can be replaced with
-/// a G_UZP1 or G_UZP2 instruction.
-///
-/// \param [in] MI - The shuffle vector instruction.
-/// \param [out] MatchInfo - Either G_UZP1 or G_UZP2 on success.
-static bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchUZP(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
   unsigned WhichResult;
   ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
   Register Dst = MI.getOperand(0).getReg();
   unsigned NumElts = MRI.getType(Dst).getNumElements();
   if (!isUZPMask(ShuffleMask, NumElts, WhichResult))
     return false;
   unsigned Opc = (WhichResult == 0) ? AArch64::G_UZP1 : AArch64::G_UZP2;
   Register V1 = MI.getOperand(1).getReg();
   Register V2 = MI.getOperand(2).getReg();
   MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
   return true;
 }
 
-static bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchZip(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
   unsigned WhichResult;
   ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
   Register Dst = MI.getOperand(0).getReg();
   unsigned NumElts = MRI.getType(Dst).getNumElements();
   if (!isZipMask(ShuffleMask, NumElts, WhichResult))
     return false;
   unsigned Opc = (WhichResult == 0) ? AArch64::G_ZIP1 : AArch64::G_ZIP2;
   Register V1 = MI.getOperand(1).getReg();
   Register V2 = MI.getOperand(2).getReg();
   MatchInfo = ShuffleVectorPseudo(Opc, Dst, {V1, V2});
   return true;
 }
 
-/// Helper function for matchDup.
-static bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI,
-                                        MachineRegisterInfo &MRI,
-                                        ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchDupFromInsertVectorElt(
+    int Lane, MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   if (Lane != 0)
     return false;
 
   // Try to match a vector splat operation into a dup instruction.
   // We're looking for this pattern:
   //
   // %scalar:gpr(s64) = COPY $x0
   // %undef:fpr(<2 x s64>) = G_IMPLICIT_DEF
if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ICst(Index)) || Index)
     return false;
 
   MatchInfo = ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(),
                                   {InsMI->getOperand(2).getReg()});
   return true;
 }
 
 /// Helper function for matchDup.
-static bool matchDupFromBuildVector(int Lane, MachineInstr &MI,
-                                    MachineRegisterInfo &MRI,
-                                    ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchDupFromBuildVector(
+    int Lane, MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(Lane >= 0 && "Expected positive lane?");
   // Test if the LHS is a BUILD_VECTOR. If it is, then we can just reference the
   // lane's definition directly.
   auto *BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR,
                                   MI.getOperand(1).getReg(), MRI);
   if (!BuildVecMI)
     return false;
   Register Reg = BuildVecMI->getOperand(Lane + 1).getReg();
   MatchInfo =
       ShuffleVectorPseudo(AArch64::G_DUP, MI.getOperand(0).getReg(), {Reg});
   return true;
 }
 
-static bool matchDup(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchDup(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
   auto MaybeLane = getSplatIndex(MI);
   if (!MaybeLane)
     return false;
   int Lane = *MaybeLane;
   // If this is undef splat, generate it via "just" vdup, if possible.
   if (Lane < 0)
     Lane = 0;
-  if (matchDupFromInsertVectorElt(Lane, MI, MRI, MatchInfo))
+  if (matchDupFromInsertVectorElt(Lane, MI, MatchInfo))
     return true;
-  if (matchDupFromBuildVector(Lane, MI, MRI, MatchInfo))
+  if (matchDupFromBuildVector(Lane, MI, MatchInfo))
     return true;
   return false;
 }
 
-static bool matchEXT(MachineInstr &MI, MachineRegisterInfo &MRI,
-                     ShuffleVectorPseudo &MatchInfo) {
+bool AArch64PostLegalizerCombinerHelper::matchEXT(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
   Register Dst = MI.getOperand(0).getReg();
   auto ExtInfo = getExtMask(MI.getOperand(3).getShuffleMask(),
                             MRI.getType(Dst).getNumElements());
   if (!ExtInfo)
     return false;
   bool ReverseExt;
   uint64_t Imm;
   std::tie(ReverseExt, Imm) = *ExtInfo;
   Register V1 = MI.getOperand(1).getReg();
   Register V2 = MI.getOperand(2).getReg();
   if (ReverseExt)
     std::swap(V1, V2);
   uint64_t ExtFactor = MRI.getType(V1).getScalarSizeInBits() / 8;
   Imm *= ExtFactor;
   MatchInfo = ShuffleVectorPseudo(AArch64::G_EXT, Dst, {V1, V2, Imm});
   return true;
 }
 
-/// Replace a G_SHUFFLE_VECTOR instruction with a pseudo.
-/// \p Opc is the opcode to use. \p MI is the G_SHUFFLE_VECTOR.
-static bool applyShuffleVectorPseudo(MachineInstr &MI,
-                                     ShuffleVectorPseudo &MatchInfo) {
-  MachineIRBuilder MIRBuilder(MI);
-  MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps);
+bool AArch64PostLegalizerCombinerHelper::applyShuffleVectorPseudo(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
+  Builder.setInstr(MI);
+  Builder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps);
   MI.eraseFromParent();
   return true;
 }
 
-/// Replace a G_SHUFFLE_VECTOR instruction with G_EXT.
-/// Special-cased because the constant operand must be emitted as a G_CONSTANT
-/// for the imported tablegen patterns to work.
-static bool applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
-  MachineIRBuilder MIRBuilder(MI);
+bool AArch64PostLegalizerCombinerHelper::applyEXT(
+    MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) {
+  Builder.setInstr(MI);
   // Tablegen patterns expect an i32 G_CONSTANT as the final op.
   auto Cst =
-      MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm());
-  MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst},
-                        {MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst});
+      Builder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm());
+  Builder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst},
   MI.eraseFromParent();
   return true;
 }
 
+class AArch64PostLegalizerCombinerHelperState {
+protected:
+  AArch64PostLegalizerCombinerHelper &Helper;
+
+public:
+  AArch64PostLegalizerCombinerHelperState(
+      AArch64PostLegalizerCombinerHelper &Helper)
+      : Helper(Helper) {}
+};
+
 #define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
 #include "AArch64GenPostLegalizeGICombiner.inc"
 #undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
 
 namespace {
 #define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
 #include "AArch64GenPostLegalizeGICombiner.inc"
 #undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
                        MachineIRBuilder &B) const override;
 };
 
 bool AArch64PostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
                                                MachineInstr &MI,
                                                MachineIRBuilder &B) const {
   const auto *LI =
       MI.getParent()->getParent()->getSubtarget().getLegalizerInfo();
-  CombinerHelper Helper(Observer, B, KB, MDT, LI);
-  AArch64GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg);
+  AArch64PostLegalizerCombinerHelper Helper(Observer, B, KB, MDT, LI);
+  AArch64GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
   return Generated.tryCombineAll(Observer, MI, B, Helper);
 }
 
 #define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
 #include "AArch64GenPostLegalizeGICombiner.inc"
 #undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
 
 class AArch64PostLegalizerCombiner : public MachineFunctionPass {