[mips][microMIPSr6] Implement disassembler support

[jkolek]

Summary

This patch implements disassembler support for microMIPS32r6.

[dsanders]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

34–35

I'd prefer not to cache flag values from MCSubtargetInfo. Could you do this the way hasMips32r6() does it instead?

I'd appreciate it if you could switch IsMicroMips to that style too (in a separate patch)

[dsanders]

LGTM

[dsanders]

Sorry, I think I missed something.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

828

Do we need both here? I'd expect IsMicroMips to be true when hasMicroMips32r6() is true. It may be better to move the hasMicroMips32r6() check to the else on line 849.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 
 #define DEBUG_TYPE "mips-disassembler"
 
 typedef MCDisassembler::DecodeStatus DecodeStatus;
 
 namespace {
 
 class MipsDisassembler : public MCDisassembler {
   bool IsMicroMips;
+  bool IsMicroMips32r6;
   bool IsBigEndian;
 public:
   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
       : MCDisassembler(STI, Ctx),
         IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips),
+        IsMicroMips32r6(STI.getFeatureBits() & Mips::FeatureMicroMipsR6),
         IsBigEndian(IsBigEndian) {}
 
   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
   bool hasMips32r6() const {
     return STI.getFeatureBits() & Mips::FeatureMips32r6;
   }
 

 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
                                               ArrayRef<uint8_t> Bytes,
                                               uint64_t Address,
                                               raw_ostream &VStream,
                                               raw_ostream &CStream) const {
   uint32_t Insn;
   DecodeStatus Result;
 
-  if (IsMicroMips) {
+  if (IsMicroMips || IsMicroMips32r6) {
     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 
     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
     // Calling the auto-generated decoder function.
     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
                                this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 2;
       return Result;
     }
 
     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
 
+    if (IsMicroMips) {
       DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
       // Calling the auto-generated decoder function.
       Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
                                  this, STI);
+    } else {
+      DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
+                                 this, STI);
+    }
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
     return MCDisassembler::Fail;
   }
 
   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);

lib/Target/Mips/MicroMipsR6InstrInfo.td

 }
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
+let DecoderNamespace = "MicroMips32r6" in {
 def ALUIPC_MMR6 : MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC, ISA_MICROMIPSR6;
 def AUIPC_MMR6 : MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPSR6;
 def ADDIUPC_MMR6 : MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC, ISA_MICROMIPSR6;
 def BALC_MMR6 : MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPSR6;
 def BC_MMR6 : MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPSR6;
 def JIALC_MMR6 : MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPSR6;
 def JIC_MMR6 : MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPSR6;
 def LWPC_MMR6 : MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPSR6;
+}

test/MC/Disassembler/Mips/micromips32r6.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromipsr6 | FileCheck %s
+
+# CHECK: aluipc $3, 56
+0x78 0x7f 0x00 0x38
+
+# CHECK: auipc $3, -1
+0x78 0x7e 0xff 0xff
+
+# CHECK: addiupc $4, 100
+0x78 0x80 0x00 0x19
+
+# CHECK: balc 14572256
+0xb4 0x37 0x96 0xb8
+
+# CHECK: bc 14572256
+0x94 0x37 0x96 0xb8
+
+# CHECK: jialc $5, 256
+0xa4 0x05 0x01 0x00
+
+# CHECK: jic $5, 256
+0xa0 0x05 0x01 0x00
+
+# CHECK: lwpc $2, 268
+0x78 0x48 0x00 0x43