[mips][microMIPSr6] Implement initial mapping support

[jkolek]

Summary

This patch introduces mapping support.

[dsanders]

I'm not very familiar with the mapping portion of microMIPS at the moment so I don't feel able to review this yet. All I know is that 'MM' does some magic that maps MIPS32r2 instructions to microMIPS instructions. Is there someone who is better able to review this? If not, I'll look into it and learn how this works.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

183 ↗

(On Diff #22648)

As mentioned in D8386, I would expect isMicroMips(STI) to be true whenever isMicroMips32r6(STI) is.

[zoran.jovanovic]

LGTM.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

183 ↗

(On Diff #23163)

Is it possible to introduce anf use isMips32r6 instead of isMicroMips32r6?

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

EncodeInstruction(const MCInst &MI, raw_ostream &OS,
   // Check for unimplemented opcodes.
   // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
   // so we have to special check for them.
   unsigned Opcode = TmpInst.getOpcode();
   if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
       (Opcode != Mips::SLL_MM) && !Binary)
     llvm_unreachable("unimplemented opcode in EncodeInstruction()");
 
-  if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
-    int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
+  if (isMicroMips(STI)) {
+    int NewOpcode = isMips32r6(STI) ?
+                    Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6) :
+                    Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
     if (NewOpcode != -1) {
       if (Fixups.size() > N)
         Fixups.pop_back();
       Opcode = NewOpcode;
       TmpInst.setOpcode (NewOpcode);
       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
     }
   }

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

+//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes microMIPS32r6 instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class MMR6Arch<string opstr> {
+  string Arch = "micromipsr6";
+  string BaseOpcode = opstr;
+}

llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td

 //=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes Mips32r6 instruction formats.
 //
 //===----------------------------------------------------------------------===//
 
+class R6MMR6Rel;
+
+def MipsR62MicroMipsR6 : InstrMapping {
+  let FilterClass = "R6MMR6Rel";
+  // Instructions with the same BaseOpcode and isNVStore values form a row.
+  let RowFields = ["BaseOpcode"];
+  // Instructions with the same predicate sense form a column.
+  let ColFields = ["Arch"];
+  // The key column is the unpredicated instructions.
+  let KeyCol = ["mipsr6"];
+  // Value columns are PredSense=true and PredSense=false
+  let ValueCols = [["mipsr6"], ["micromipsr6"]];
+}
+
+class MipsR6Arch<string opstr> {
+  string Arch = "mipsr6";
+  string BaseOpcode = opstr;
+}
+
 class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
                    PredicateControl {
   let DecoderNamespace = "Mips32r6_64r6";
   let EncodingPredicates = [HasStdEnc];
 }
 
 //===----------------------------------------------------------------------===//
 //