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Differential D84879

[X86] Separate CPU Feature lists in X86.td between architecture features and tuning features
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Authored by craig.topper on Jul 29 2020, 11:29 AM.

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RKSimon
spatel
echristo
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rG3ad09fd03c51: [X86] Separate CPU Feature lists in X86.td between architecture features and…
Summary

After the recent change to the tuning settings for pentium4 to improve our default 32-bit behavior, I've decided to see about implementing -mtune support. This way we could have a default architecture CPU of "pentium4" or "x86-64" and a default tuning cpu of "generic". And we could change our "pentium4" tuning settings back to what they were before.

As a step to supporting this, this patch separates all of the features lists for the CPUs into 2 lists. I'm using the Proc class and a new ProcModel class to concat the 2 lists before passing to the target independent ProcessorModel. Future work to truly support mtune would change ProcessorModel to take 2 lists separately. I've diffed the X86GenSubtargetInfo.inc file before and after this patch to ensure that the final feature list for the CPUs isn't changed.

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Event Timeline

craig.topper created this revision.Jul 29 2020, 11:29 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 29 2020, 11:29 AM
Herald added subscribers: jfb, hiraditya. · View Herald Transcript
craig.topper requested review of this revision.Jul 29 2020, 11:29 AM
craig.topper added inline comments.
llvm/lib/Target/X86/X86.td
620

Oops. I left some tuning flags in here. I'll fix and upload a new patch soon.

craig.topper updated this revision to Diff 281688.Jul 29 2020, 11:34 AM

Fixed BDWAdditionalFeatures

RKSimon added inline comments.Jul 29 2020, 11:35 AM
llvm/lib/Target/X86/X86.td
562

I keep forgetting to ask - why do targets without AVX implement FeatureInsertVZEROUPPER?

craig.topper added inline comments.Jul 29 2020, 11:58 AM
llvm/lib/Target/X86/X86.td
562

It starts with an assumption that "-mavx" without a -march should insert vzeroupper. Since in that case the CPU will be pentium4 or x86-64 so those CPUs need the feature. Maybe also i486 or i686 if you're on the BSD that uses those as the default 32-bit CPU. After that it was just to apply consistent behavior if you wrote something like "-march=nehalem -mavx" for some reason.

RKSimon accepted this revision.Jul 30 2020, 12:43 PM

LGTM - thanks for taking this on!

This revision is now accepted and ready to land.Jul 30 2020, 12:43 PM
Closed by commit rG3ad09fd03c51: [X86] Separate CPU Feature lists in X86.td between architecture features and… (authored by craig.topper). · Explain WhyJul 30 2020, 5:20 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG3ad09fd03c51: [X86] Separate CPU Feature lists in X86.td between architecture features and….

Revision Contents

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llvm/
lib/
Target/
X86/
773 lines

Diff 281681

llvm/lib/Target/X86/X86.td

Show First 20 Lines • Show All 541 Lines • ▼ Show 20 Lines
include "X86SchedSkylakeServer.td" include "X86SchedSkylakeServer.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// X86 Processor Feature Lists // X86 Processor Feature Lists
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ProcessorFeatures { def ProcessorFeatures {
// Nehalem // Nehalem
list<SubtargetFeature> NHMInheritableFeatures = [FeatureX87, list<SubtargetFeature> NHMFeatures = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSE42, FeatureSSE42,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeaturePOPCNT, FeaturePOPCNT,
FeatureLAHFSAHF, FeatureLAHFSAHF];
FeatureMacroFusion, list<SubtargetFeature> NHMTuning = [FeatureMacroFusion,
FeatureInsertVZEROUPPER]; FeatureInsertVZEROUPPER];
RKSimonUnsubmitted
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I keep forgetting to ask - why do targets without AVX implement FeatureInsertVZEROUPPER?

RKSimon: I keep forgetting to ask - why do targets without AVX implement FeatureInsertVZEROUPPER?
craig.topperAuthorUnsubmitted
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It starts with an assumption that "-mavx" without a -march should insert vzeroupper. Since in that case the CPU will be pentium4 or x86-64 so those CPUs need the feature. Maybe also i486 or i686 if you're on the BSD that uses those as the default 32-bit CPU. After that it was just to apply consistent behavior if you wrote something like "-march=nehalem -mavx" for some reason.

craig.topper: It starts with an assumption that "-mavx" without a -march should insert vzeroupper. Since in…
list<SubtargetFeature> NHMSpecificFeatures = [];
list<SubtargetFeature> NHMFeatures =
!listconcat(NHMInheritableFeatures, NHMSpecificFeatures);
// Westmere // Westmere
list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL]; list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
list<SubtargetFeature> WSMSpecificFeatures = []; list<SubtargetFeature> WSMTuning = NHMTuning;
list<SubtargetFeature> WSMInheritableFeatures =
!listconcat(NHMInheritableFeatures, WSMAdditionalFeatures);
list<SubtargetFeature> WSMFeatures = list<SubtargetFeature> WSMFeatures =
!listconcat(WSMInheritableFeatures, WSMSpecificFeatures); !listconcat(NHMFeatures, WSMAdditionalFeatures);
// Sandybridge // Sandybridge
list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX, list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
FeatureSlowDivide64,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT, FeatureXSAVEOPT];
list<SubtargetFeature> SNBTuning = [FeatureMacroFusion,
FeatureSlow3OpsLEA, FeatureSlow3OpsLEA,
FeatureSlowDivide64,
FeatureSlowUAMem32,
FeatureFastScalarFSQRT, FeatureFastScalarFSQRT,
FeatureFastSHLDRotate, FeatureFastSHLDRotate,
FeatureFast15ByteNOP]; FeatureFast15ByteNOP,
list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32, FeaturePOPCNTFalseDeps,
FeaturePOPCNTFalseDeps]; FeatureInsertVZEROUPPER];
list<SubtargetFeature> SNBInheritableFeatures =
!listconcat(WSMInheritableFeatures, SNBAdditionalFeatures);
list<SubtargetFeature> SNBFeatures = list<SubtargetFeature> SNBFeatures =
!listconcat(SNBInheritableFeatures, SNBSpecificFeatures); !listconcat(WSMFeatures, SNBAdditionalFeatures);
// Ivybridge // Ivybridge
list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND, list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
FeatureF16C, FeatureF16C,
FeatureFSGSBase]; FeatureFSGSBase];
list<SubtargetFeature> IVBSpecificFeatures = [FeatureSlowUAMem32, list<SubtargetFeature> IVBTuning = SNBTuning;
FeaturePOPCNTFalseDeps];
list<SubtargetFeature> IVBInheritableFeatures =
!listconcat(SNBInheritableFeatures, IVBAdditionalFeatures);
list<SubtargetFeature> IVBFeatures = list<SubtargetFeature> IVBFeatures =
!listconcat(IVBInheritableFeatures, IVBSpecificFeatures); !listconcat(SNBFeatures, IVBAdditionalFeatures);
// Haswell // Haswell
list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2, list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
FeatureBMI, FeatureBMI,
FeatureBMI2, FeatureBMI2,
FeatureERMSB, FeatureERMSB,
FeatureFMA, FeatureFMA,
FeatureINVPCID, FeatureINVPCID,
FeatureLZCNT, FeatureLZCNT,
FeatureMOVBE, FeatureMOVBE];
FeatureFastVariableShuffle]; list<SubtargetFeature> HSWTuning = [FeatureMacroFusion,
list<SubtargetFeature> HSWSpecificFeatures = [FeaturePOPCNTFalseDeps, FeatureSlow3OpsLEA,
FeatureLZCNTFalseDeps]; FeatureSlowDivide64,
list<SubtargetFeature> HSWInheritableFeatures = FeatureFastScalarFSQRT,
!listconcat(IVBInheritableFeatures, HSWAdditionalFeatures); FeatureFastSHLDRotate,
FeatureFast15ByteNOP,
FeatureFastVariableShuffle,
FeaturePOPCNTFalseDeps,
FeatureLZCNTFalseDeps,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> HSWFeatures = list<SubtargetFeature> HSWFeatures =
!listconcat(HSWInheritableFeatures, HSWSpecificFeatures); !listconcat(IVBFeatures, HSWAdditionalFeatures);
// Broadwell // Broadwell
list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX, list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
FeatureRDSEED, FeatureRDSEED,
FeaturePRFCHW]; FeaturePRFCHW,
list<SubtargetFeature> BDWSpecificFeatures = [FeaturePOPCNTFalseDeps, FeatureMacroFusion,
craig.topperAuthorUnsubmitted
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Oops. I left some tuning flags in here. I'll fix and upload a new patch soon.

craig.topper: Oops. I left some tuning flags in here. I'll fix and upload a new patch soon.
FeatureLZCNTFalseDeps]; FeatureSlow3OpsLEA,
list<SubtargetFeature> BDWInheritableFeatures = FeatureSlowDivide64,
!listconcat(HSWInheritableFeatures, BDWAdditionalFeatures); FeatureFastScalarFSQRT,
FeatureFastSHLDRotate,
FeatureFast15ByteNOP,
FeatureFastVariableShuffle,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> BDWTuning = HSWTuning;
list<SubtargetFeature> BDWFeatures = list<SubtargetFeature> BDWFeatures =
!listconcat(BDWInheritableFeatures, BDWSpecificFeatures); !listconcat(HSWFeatures, BDWAdditionalFeatures);
// Skylake // Skylake
list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES, list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVES, FeatureXSAVES,
FeatureCLFLUSHOPT, FeatureCLFLUSHOPT,
FeatureFastVectorFSQRT];
list<SubtargetFeature> SKLSpecificFeatures = [FeatureHasFastGather,
FeaturePOPCNTFalseDeps,
FeatureSGX]; FeatureSGX];
list<SubtargetFeature> SKLInheritableFeatures = list<SubtargetFeature> SKLTuning = [FeatureHasFastGather,
!listconcat(BDWInheritableFeatures, SKLAdditionalFeatures); FeatureMacroFusion,
FeatureSlow3OpsLEA,
FeatureSlowDivide64,
FeatureFastScalarFSQRT,
FeatureFastVectorFSQRT,
FeatureFastSHLDRotate,
FeatureFast15ByteNOP,
FeatureFastVariableShuffle,
FeaturePOPCNTFalseDeps,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> SKLFeatures = list<SubtargetFeature> SKLFeatures =
!listconcat(SKLInheritableFeatures, SKLSpecificFeatures); !listconcat(BDWFeatures, SKLAdditionalFeatures);
// Skylake-AVX512 // Skylake-AVX512
list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAVX512, list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,
FeaturePrefer256Bit, FeatureXSAVEC,
FeatureXSAVES,
FeatureCLFLUSHOPT,
FeatureAVX512,
FeatureCDI, FeatureCDI,
FeatureDQI, FeatureDQI,
FeatureBWI, FeatureBWI,
FeatureVLX, FeatureVLX,
FeaturePKU, FeaturePKU,
FeatureCLWB]; FeatureCLWB];
list<SubtargetFeature> SKXSpecificFeatures = [FeatureHasFastGather, list<SubtargetFeature> SKXTuning = [FeatureHasFastGather,
FeaturePOPCNTFalseDeps]; FeatureMacroFusion,
list<SubtargetFeature> SKXInheritableFeatures = FeatureSlow3OpsLEA,
!listconcat(SKLInheritableFeatures, SKXAdditionalFeatures); FeatureSlowDivide64,
FeatureFastScalarFSQRT,
FeatureFastVectorFSQRT,
FeatureFastSHLDRotate,
FeatureFast15ByteNOP,
FeatureFastVariableShuffle,
FeaturePrefer256Bit,
FeaturePOPCNTFalseDeps,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> SKXFeatures = list<SubtargetFeature> SKXFeatures =
!listconcat(SKXInheritableFeatures, SKXSpecificFeatures); !listconcat(BDWFeatures, SKXAdditionalFeatures);
// Cascadelake // Cascadelake
list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI]; list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
list<SubtargetFeature> CLXSpecificFeatures = [FeatureHasFastGather, list<SubtargetFeature> CLXTuning = SKXTuning;
FeaturePOPCNTFalseDeps];
list<SubtargetFeature> CLXInheritableFeatures =
!listconcat(SKXInheritableFeatures, CLXAdditionalFeatures);
list<SubtargetFeature> CLXFeatures = list<SubtargetFeature> CLXFeatures =
!listconcat(CLXInheritableFeatures, CLXSpecificFeatures); !listconcat(SKXFeatures, CLXAdditionalFeatures);
// Cooperlake // Cooperlake
list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16]; list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
list<SubtargetFeature> CPXSpecificFeatures = [FeatureHasFastGather, list<SubtargetFeature> CPXTuning = SKXTuning;
FeaturePOPCNTFalseDeps];
list<SubtargetFeature> CPXInheritableFeatures =
!listconcat(CLXInheritableFeatures, CPXAdditionalFeatures);
list<SubtargetFeature> CPXFeatures = list<SubtargetFeature> CPXFeatures =
!listconcat(CPXInheritableFeatures, CPXSpecificFeatures); !listconcat(CLXFeatures, CPXAdditionalFeatures);
// Cannonlake // Cannonlake
list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512, list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
FeaturePrefer256Bit,
FeatureCDI, FeatureCDI,
FeatureDQI, FeatureDQI,
FeatureBWI, FeatureBWI,
FeatureVLX, FeatureVLX,
FeaturePKU, FeaturePKU,
FeatureVBMI, FeatureVBMI,
FeatureIFMA, FeatureIFMA,
FeatureSHA, FeatureSHA];
FeatureSGX]; list<SubtargetFeature> CNLTuning = [FeatureHasFastGather,
list<SubtargetFeature> CNLSpecificFeatures = [FeatureHasFastGather]; FeatureMacroFusion,
list<SubtargetFeature> CNLInheritableFeatures = FeatureSlow3OpsLEA,
!listconcat(SKLInheritableFeatures, CNLAdditionalFeatures); FeatureSlowDivide64,
FeatureFastScalarFSQRT,
FeatureFastVectorFSQRT,
FeatureFastSHLDRotate,
FeatureFast15ByteNOP,
FeatureFastVariableShuffle,
FeaturePrefer256Bit,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> CNLFeatures = list<SubtargetFeature> CNLFeatures =
!listconcat(CNLInheritableFeatures, CNLSpecificFeatures); !listconcat(SKLFeatures, CNLAdditionalFeatures);
// Icelake // Icelake
list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG, list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
FeatureVAES, FeatureVAES,
FeatureVBMI2, FeatureVBMI2,
FeatureVNNI, FeatureVNNI,
FeatureVPCLMULQDQ, FeatureVPCLMULQDQ,
FeatureVPOPCNTDQ, FeatureVPOPCNTDQ,
FeatureGFNI, FeatureGFNI,
FeatureCLWB, FeatureCLWB,
FeatureRDPID]; FeatureRDPID];
list<SubtargetFeature> ICLSpecificFeatures = [FeatureHasFastGather]; list<SubtargetFeature> ICLTuning = CNLTuning;
list<SubtargetFeature> ICLInheritableFeatures =
!listconcat(CNLInheritableFeatures, ICLAdditionalFeatures);
list<SubtargetFeature> ICLFeatures = list<SubtargetFeature> ICLFeatures =
!listconcat(ICLInheritableFeatures, ICLSpecificFeatures); !listconcat(CNLFeatures, ICLAdditionalFeatures);
// Icelake Server // Icelake Server
list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG, list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG,
FeatureWBNOINVD, FeatureWBNOINVD];
FeatureHasFastGather]; list<SubtargetFeature> ICXTuning = CNLTuning;
list<SubtargetFeature> ICXFeatures = list<SubtargetFeature> ICXFeatures =
!listconcat(ICLInheritableFeatures, ICXSpecificFeatures); !listconcat(ICLFeatures, ICXAdditionalFeatures);
//Tigerlake //Tigerlake
list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT, list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
FeatureMOVDIRI, FeatureMOVDIRI,
FeatureMOVDIR64B, FeatureMOVDIR64B,
FeatureSHSTK]; FeatureSHSTK];
list<SubtargetFeature> TGLSpecificFeatures = [FeatureHasFastGather]; list<SubtargetFeature> TGLTuning = CNLTuning;
list<SubtargetFeature> TGLInheritableFeatures =
!listconcat(TGLAdditionalFeatures ,TGLSpecificFeatures);
list<SubtargetFeature> TGLFeatures = list<SubtargetFeature> TGLFeatures =
!listconcat(ICLFeatures, TGLInheritableFeatures ); !listconcat(ICLFeatures, TGLAdditionalFeatures );
// Atom // Atom
list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87, list<SubtargetFeature> AtomFeatures = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSSE3, FeatureSSSE3,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureMOVBE, FeatureMOVBE,
FeatureSlowTwoMemOps, FeatureLAHFSAHF];
FeatureLAHFSAHF, list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> AtomSpecificFeatures = [ProcIntelAtom,
FeatureSlowUAMem16, FeatureSlowUAMem16,
FeatureLEAForSP, FeatureLEAForSP,
FeatureSlowDivide32, FeatureSlowDivide32,
FeatureSlowDivide64, FeatureSlowDivide64,
FeatureSlowTwoMemOps,
FeatureLEAUsesAG, FeatureLEAUsesAG,
FeaturePadShortFunctions]; FeaturePadShortFunctions,
list<SubtargetFeature> AtomFeatures = FeatureInsertVZEROUPPER];
!listconcat(AtomInheritableFeatures, AtomSpecificFeatures);
// Silvermont // Silvermont
list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42, list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
FeaturePOPCNT, FeaturePOPCNT,
FeaturePCLMUL, FeaturePCLMUL,
FeaturePRFCHW, FeaturePRFCHW,
FeatureRDRAND];
list<SubtargetFeature> SLMTuning = [ProcIntelSLM,
FeatureSlowTwoMemOps,
FeatureSlowLEA, FeatureSlowLEA,
FeatureSlowIncDec, FeatureSlowIncDec,
FeatureRDRAND];
list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM,
FeatureSlowDivide64, FeatureSlowDivide64,
FeatureSlowPMULLD, FeatureSlowPMULLD,
FeatureFast7ByteNOP, FeatureFast7ByteNOP,
FeaturePOPCNTFalseDeps]; FeaturePOPCNTFalseDeps,
list<SubtargetFeature> SLMInheritableFeatures = FeatureInsertVZEROUPPER];
!listconcat(AtomInheritableFeatures, SLMAdditionalFeatures);
list<SubtargetFeature> SLMFeatures = list<SubtargetFeature> SLMFeatures =
!listconcat(SLMInheritableFeatures, SLMSpecificFeatures); !listconcat(AtomFeatures, SLMAdditionalFeatures);
// Goldmont // Goldmont
list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES, list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
FeatureSHA, FeatureSHA,
FeatureRDSEED, FeatureRDSEED,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT, FeatureXSAVEOPT,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVES, FeatureXSAVES,
FeatureCLFLUSHOPT, FeatureCLFLUSHOPT,
FeatureFSGSBase]; FeatureFSGSBase];
list<SubtargetFeature> GLMSpecificFeatures = [FeatureUseGLMDivSqrtCosts, list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts,
FeaturePOPCNTFalseDeps]; FeatureSlowTwoMemOps,
list<SubtargetFeature> GLMInheritableFeatures = FeatureSlowLEA,
!listconcat(SLMInheritableFeatures, GLMAdditionalFeatures); FeatureSlowIncDec,
FeaturePOPCNTFalseDeps,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> GLMFeatures = list<SubtargetFeature> GLMFeatures =
!listconcat(GLMInheritableFeatures, GLMSpecificFeatures); !listconcat(SLMFeatures, GLMAdditionalFeatures);
// Goldmont Plus // Goldmont Plus
list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE, list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
FeatureRDPID, FeatureRDPID,
FeatureSGX]; FeatureSGX];
list<SubtargetFeature> GLPSpecificFeatures = [FeatureUseGLMDivSqrtCosts]; list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts,
list<SubtargetFeature> GLPInheritableFeatures = FeatureSlowTwoMemOps,
!listconcat(GLMInheritableFeatures, GLPAdditionalFeatures); FeatureSlowLEA,
FeatureSlowIncDec,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> GLPFeatures = list<SubtargetFeature> GLPFeatures =
!listconcat(GLPInheritableFeatures, GLPSpecificFeatures); !listconcat(GLMFeatures, GLPAdditionalFeatures);
// Tremont // Tremont
list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB, list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
FeatureGFNI]; FeatureGFNI];
list<SubtargetFeature> TRMSpecificFeatures = [FeatureUseGLMDivSqrtCosts]; list<SubtargetFeature> TRMTuning = GLPTuning;
list<SubtargetFeature> TRMInheritableFeatures =
!listconcat(GLPInheritableFeatures, TRMAdditionalFeatures);
list<SubtargetFeature> TRMFeatures = list<SubtargetFeature> TRMFeatures =
!listconcat(TRMInheritableFeatures, TRMSpecificFeatures); !listconcat(GLPFeatures, TRMAdditionalFeatures);
// Knights Landing // Knights Landing
list<SubtargetFeature> KNLFeatures = [FeatureX87, list<SubtargetFeature> KNLFeatures = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeaturePOPCNT, FeaturePOPCNT,
FeatureSlowDivide64,
FeaturePCLMUL, FeaturePCLMUL,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT, FeatureXSAVEOPT,
FeatureLAHFSAHF, FeatureLAHFSAHF,
FeatureSlow3OpsLEA,
FeatureSlowIncDec,
FeatureAES, FeatureAES,
FeatureRDRAND, FeatureRDRAND,
FeatureF16C, FeatureF16C,
FeatureFSGSBase, FeatureFSGSBase,
FeatureAVX512, FeatureAVX512,
FeatureERI, FeatureERI,
FeatureCDI, FeatureCDI,
FeaturePFI, FeaturePFI,
FeaturePREFETCHWT1, FeaturePREFETCHWT1,
FeatureADX, FeatureADX,
FeatureRDSEED, FeatureRDSEED,
FeatureMOVBE, FeatureMOVBE,
FeatureLZCNT, FeatureLZCNT,
FeatureBMI, FeatureBMI,
FeatureBMI2, FeatureBMI2,
FeatureFMA, FeatureFMA,
FeaturePRFCHW, FeaturePRFCHW];
FeaturePreferMaskRegisters, list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64,
FeatureSlow3OpsLEA,
FeatureSlowIncDec,
FeatureSlowTwoMemOps, FeatureSlowTwoMemOps,
FeaturePreferMaskRegisters,
FeatureHasFastGather, FeatureHasFastGather,
FeatureSlowPMADDWD]; FeatureSlowPMADDWD];
// TODO Add AVX5124FMAPS/AVX5124VNNIW features // TODO Add AVX5124FMAPS/AVX5124VNNIW features
list<SubtargetFeature> KNMFeatures = list<SubtargetFeature> KNMFeatures =
!listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
// Barcelona // Barcelona
list<SubtargetFeature> BarcelonaInheritableFeatures = [FeatureX87, list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureSSE4A, FeatureSSE4A,
Feature3DNowA, Feature3DNowA,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeaturePRFCHW, FeaturePRFCHW,
FeatureLZCNT, FeatureLZCNT,
FeaturePOPCNT, FeaturePOPCNT,
FeatureSlowSHLD,
FeatureLAHFSAHF, FeatureLAHFSAHF,
FeatureCMOV, FeatureCMOV,
Feature64Bit, Feature64Bit];
FeatureFastScalarShiftMasks, list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks,
FeatureSlowSHLD,
FeatureInsertVZEROUPPER]; FeatureInsertVZEROUPPER];
list<SubtargetFeature> BarcelonaFeatures = BarcelonaInheritableFeatures;
// Bobcat // Bobcat
list<SubtargetFeature> BtVer1InheritableFeatures = [FeatureX87, list<SubtargetFeature> BtVer1Features = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSSE3, FeatureSSSE3,
FeatureSSE4A, FeatureSSE4A,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeaturePRFCHW, FeaturePRFCHW,
FeatureLZCNT, FeatureLZCNT,
FeaturePOPCNT, FeaturePOPCNT,
FeatureSlowSHLD, FeatureLAHFSAHF];
FeatureLAHFSAHF, list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP,
FeatureFast15ByteNOP,
FeatureFastScalarShiftMasks, FeatureFastScalarShiftMasks,
FeatureFastVectorShiftMasks]; FeatureFastVectorShiftMasks,
list<SubtargetFeature> BtVer1SpecificFeatures = [FeatureInsertVZEROUPPER]; FeatureSlowSHLD,
list<SubtargetFeature> BtVer1Features = FeatureInsertVZEROUPPER];
!listconcat(BtVer1InheritableFeatures, BtVer1SpecificFeatures);
// Jaguar // Jaguar
list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX, list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
FeatureAES, FeatureAES,
FeaturePCLMUL, FeaturePCLMUL,
FeatureBMI, FeatureBMI,
FeatureF16C, FeatureF16C,
FeatureMOVBE, FeatureMOVBE,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT]; FeatureXSAVEOPT];
list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT, list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT,
FeatureFastBEXTR, FeatureFastBEXTR,
FeatureFastHorizontalOps]; FeatureFastHorizontalOps,
list<SubtargetFeature> BtVer2InheritableFeatures = FeatureFast15ByteNOP,
!listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures); FeatureFastScalarShiftMasks,
FeatureFastVectorShiftMasks,
FeatureSlowSHLD];
list<SubtargetFeature> BtVer2Features = list<SubtargetFeature> BtVer2Features =
!listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures); !listconcat(BtVer1Features, BtVer2AdditionalFeatures);
// Bulldozer // Bulldozer
list<SubtargetFeature> BdVer1InheritableFeatures = [FeatureX87, list<SubtargetFeature> BdVer1Features = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureXOP, FeatureXOP,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureAES, FeatureAES,
FeaturePRFCHW, FeaturePRFCHW,
FeaturePCLMUL, FeaturePCLMUL,
FeatureMMX, FeatureMMX,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
FeatureLZCNT, FeatureLZCNT,
FeaturePOPCNT, FeaturePOPCNT,
FeatureXSAVE, FeatureXSAVE,
FeatureLWP, FeatureLWP,
FeatureSlowSHLD, FeatureLAHFSAHF];
FeatureLAHFSAHF, list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD,
FeatureFast11ByteNOP, FeatureFast11ByteNOP,
FeatureFastScalarShiftMasks, FeatureFastScalarShiftMasks,
FeatureBranchFusion, FeatureBranchFusion,
FeatureInsertVZEROUPPER]; FeatureInsertVZEROUPPER];
list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures;
// PileDriver // PileDriver
list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C, list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
FeatureBMI, FeatureBMI,
FeatureTBM, FeatureTBM,
FeatureFMA, FeatureFMA,
FeatureFastBEXTR]; FeatureFastBEXTR];
list<SubtargetFeature> BdVer2InheritableFeatures = list<SubtargetFeature> BdVer2Tuning = BdVer1Tuning;
!listconcat(BdVer1InheritableFeatures, BdVer2AdditionalFeatures); list<SubtargetFeature> BdVer2Features =
list<SubtargetFeature> BdVer2Features = BdVer2InheritableFeatures; !listconcat(BdVer1Features, BdVer2AdditionalFeatures);
// Steamroller // Steamroller
list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT, list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
FeatureFSGSBase]; FeatureFSGSBase];
list<SubtargetFeature> BdVer3InheritableFeatures = list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning;
!listconcat(BdVer2InheritableFeatures, BdVer3AdditionalFeatures); list<SubtargetFeature> BdVer3Features =
list<SubtargetFeature> BdVer3Features = BdVer3InheritableFeatures; !listconcat(BdVer2Features, BdVer3AdditionalFeatures);
// Excavator // Excavator
list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2, list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
FeatureBMI2, FeatureBMI2,
FeatureMOVBE, FeatureMOVBE,
FeatureRDRAND, FeatureRDRAND,
FeatureMWAITX]; FeatureMWAITX];
list<SubtargetFeature> BdVer4InheritableFeatures = list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning;
!listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures); list<SubtargetFeature> BdVer4Features =
list<SubtargetFeature> BdVer4Features = BdVer4InheritableFeatures; !listconcat(BdVer3Features, BdVer4AdditionalFeatures);
// AMD Zen Processors common ISAs // AMD Zen Processors common ISAs
list<SubtargetFeature> ZNFeatures = [FeatureADX, list<SubtargetFeature> ZNFeatures = [FeatureADX,
FeatureAES, FeatureAES,
FeatureAVX2, FeatureAVX2,
FeatureBMI, FeatureBMI,
FeatureBMI2, FeatureBMI2,
FeatureCLFLUSHOPT, FeatureCLFLUSHOPT,
FeatureCLZERO, FeatureCLZERO,
FeatureCMOV, FeatureCMOV,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureF16C, FeatureF16C,
FeatureFMA, FeatureFMA,
FeatureFSGSBase, FeatureFSGSBase,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
FeatureFastLZCNT,
FeatureLAHFSAHF, FeatureLAHFSAHF,
FeatureLZCNT, FeatureLZCNT,
FeatureFastBEXTR,
FeatureFast15ByteNOP,
FeatureBranchFusion,
FeatureFastScalarShiftMasks,
FeatureMMX, FeatureMMX,
FeatureMOVBE, FeatureMOVBE,
FeatureMWAITX, FeatureMWAITX,
FeaturePCLMUL, FeaturePCLMUL,
FeaturePOPCNT, FeaturePOPCNT,
FeaturePRFCHW, FeaturePRFCHW,
FeatureRDRAND, FeatureRDRAND,
FeatureRDSEED, FeatureRDSEED,
FeatureSHA, FeatureSHA,
FeatureSSE4A, FeatureSSE4A,
FeatureSlowSHLD,
FeatureInsertVZEROUPPER,
FeatureX87, FeatureX87,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVEOPT, FeatureXSAVEOPT,
FeatureXSAVES]; FeatureXSAVES];
list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT,
FeatureFastBEXTR,
FeatureFast15ByteNOP,
FeatureBranchFusion,
FeatureFastScalarShiftMasks,
FeatureSlowSHLD,
FeatureInsertVZEROUPPER];
list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB, list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
FeatureRDPID, FeatureRDPID,
FeatureWBNOINVD]; FeatureWBNOINVD];
list<SubtargetFeature> ZN2Tuning = ZNTuning;
list<SubtargetFeature> ZN2Features = list<SubtargetFeature> ZN2Features =
!listconcat(ZNFeatures, ZN2AdditionalFeatures); !listconcat(ZNFeatures, ZN2AdditionalFeatures);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// X86 processors supported. // X86 processors supported.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features> class Proc<string Name, list<SubtargetFeature> Features,
: ProcessorModel<Name, GenericModel, Features>; list<SubtargetFeature> TuneFeatures>
: ProcessorModel<Name, GenericModel, !listconcat(Features, TuneFeatures)>;
class ProcModel<string Name, SchedMachineModel Model,
list<SubtargetFeature> Features,
list<SubtargetFeature> TuneFeatures>
: ProcessorModel<Name, Model, !listconcat(Features, TuneFeatures)>;
// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled // NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
// if i386/i486 is specifically requested. // if i386/i486 is specifically requested.
// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget // NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled. // constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled.
// It has no effect on code generation. // It has no effect on code generation.
def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16, def : Proc<"generic", [FeatureX87, FeatureCMPXCHG8B, Feature64Bit],
FeatureCMPXCHG8B, Feature64Bit, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureInsertVZEROUPPER]>; def : Proc<"i386", [FeatureX87],
def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureInsertVZEROUPPER]>; def : Proc<"i486", [FeatureX87],
def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureInsertVZEROUPPER]>; def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B],
def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureCMPXCHG8B, FeatureInsertVZEROUPPER]>; def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B],
def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureCMPXCHG8B, FeatureInsertVZEROUPPER]>; def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureCMPXCHG8B, FeatureMMX,
FeatureInsertVZEROUPPER]>; def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
FeatureCMOV, FeatureInsertVZEROUPPER]>; FeatureNOPL],
def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureCMOV, FeatureNOPL, FeatureInsertVZEROUPPER]>;
def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV,
def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureFXSR, FeatureNOPL],
FeatureMMX, FeatureCMOV, FeatureFXSR, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureNOPL, FeatureInsertVZEROUPPER]>;
foreach P = ["pentium3", "pentium3m"] in { foreach P = ["pentium3", "pentium3m"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV, FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
} }
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
// The intent is to enable it for pentium4 which is the current default // The intent is to enable it for pentium4 which is the current default
// processor in a vanilla 32-bit clang compilation when no specific // processor in a vanilla 32-bit clang compilation when no specific
// architecture is specified. This generally gives a nice performance // architecture is specified. This generally gives a nice performance
// increase on silvermont, with largely neutral behavior on other // increase on silvermont, with largely neutral behavior on other
// contemporary large core processors. // contemporary large core processors.
// pentium-m, pentium4m, prescott and nocona are included as a preventative // pentium-m, pentium4m, prescott and nocona are included as a preventative
// measure to avoid performance surprises, in case clang's default cpu // measure to avoid performance surprises, in case clang's default cpu
// changes slightly. // changes slightly.
def : ProcessorModel<"pentium-m", GenericPostRAModel, def : ProcModel<"pentium-m", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureFXSR, FeatureNOPL, FeatureCMOV],
FeatureCMOV, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
foreach P = ["pentium4", "pentium4m"] in { foreach P = ["pentium4", "pentium4m"] in {
// def : ProcessorModel<P, GenericPostRAModel, // def : ProcModel<P, GenericPostRAModel,
// [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, // [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
// FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, // FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
// FeatureCMOV, FeatureInsertVZEROUPPER]>; // [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
// Since 'pentium4' is the default 32-bit CPU on Linux and Windows, // Since 'pentium4' is the default 32-bit CPU on Linux and Windows,
// give it more modern tunings. // give it more modern tunings.
// FIXME: This wouldn't be needed if we supported mtune. // FIXME: This wouldn't be needed if we supported mtune.
def : ProcessorModel<P, SandyBridgeModel, def : ProcModel<P, SandyBridgeModel,
[FeatureX87, FeatureCMPXCHG8B, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureFXSR, FeatureNOPL, FeatureCMOV],
FeatureCMOV, FeatureInsertVZEROUPPER, [FeatureSlow3OpsLEA, FeatureSlowDivide64,
FeatureSlow3OpsLEA, FeatureSlowDivide64, FeatureSlowIncDec, FeatureMacroFusion,
FeatureSlowIncDec, FeatureMacroFusion]>; FeatureInsertVZEROUPPER]>;
} }
// Intel Quark. // Intel Quark.
def : Proc<"lakemont", [FeatureSlowUAMem16, FeatureCMPXCHG8B, def : Proc<"lakemont", [FeatureCMPXCHG8B],
FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
// Intel Core Duo. // Intel Core Duo.
def : ProcessorModel<"yonah", SandyBridgeModel, def : ProcModel<"yonah", SandyBridgeModel,
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, FeatureFXSR, FeatureNOPL, FeatureCMOV],
FeatureCMOV, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
// NetBurst. // NetBurst.
def : ProcessorModel<"prescott", GenericPostRAModel, def : ProcModel<"prescott", GenericPostRAModel,
[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, FeatureFXSR, FeatureNOPL, FeatureCMOV],
FeatureCMOV, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : ProcessorModel<"nocona", GenericPostRAModel, [ def : ProcModel<"nocona", GenericPostRAModel, [
FeatureX87, FeatureX87,
FeatureSlowUAMem16,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSE3, FeatureSSE3,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
],
[
FeatureSlowUAMem16,
FeatureInsertVZEROUPPER FeatureInsertVZEROUPPER
]>; ]>;
// Intel Core 2 Solo/Duo. // Intel Core 2 Solo/Duo.
def : ProcessorModel<"core2", SandyBridgeModel, [ def : ProcModel<"core2", SandyBridgeModel, [
FeatureX87, FeatureX87,
FeatureSlowUAMem16,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSSE3, FeatureSSSE3,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureLAHFSAHF, FeatureLAHFSAHF
],
[
FeatureMacroFusion, FeatureMacroFusion,
FeatureSlowUAMem16,
FeatureInsertVZEROUPPER FeatureInsertVZEROUPPER
]>; ]>;
def : ProcessorModel<"penryn", SandyBridgeModel, [ def : ProcModel<"penryn", SandyBridgeModel, [
FeatureX87, FeatureX87,
FeatureSlowUAMem16,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSE41, FeatureSSE41,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureLAHFSAHF, FeatureLAHFSAHF
],
[
FeatureMacroFusion, FeatureMacroFusion,
FeatureSlowUAMem16,
FeatureInsertVZEROUPPER FeatureInsertVZEROUPPER
]>; ]>;
// Atom CPUs. // Atom CPUs.
foreach P = ["bonnell", "atom"] in { foreach P = ["bonnell", "atom"] in {
def : ProcessorModel<P, AtomModel, ProcessorFeatures.AtomFeatures>; def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
ProcessorFeatures.AtomTuning>;
} }
foreach P = ["silvermont", "slm"] in { foreach P = ["silvermont", "slm"] in {
def : ProcessorModel<P, SLMModel, ProcessorFeatures.SLMFeatures>; def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,
ProcessorFeatures.SLMTuning>;
} }
def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>; def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>; ProcessorFeatures.GLMTuning>;
def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>; def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures,
ProcessorFeatures.GLPTuning>;
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
// "Arrandale" along with corei3 and corei5 // "Arrandale" along with corei3 and corei5
foreach P = ["nehalem", "corei7"] in { foreach P = ["nehalem", "corei7"] in {
def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures>; def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
ProcessorFeatures.NHMTuning>;
} }
// Westmere is the corei3/i5/i7 path from nehalem to sandybridge // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
def : ProcessorModel<"westmere", SandyBridgeModel, def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures,
ProcessorFeatures.WSMFeatures>; ProcessorFeatures.WSMTuning>;
foreach P = ["sandybridge", "corei7-avx"] in { foreach P = ["sandybridge", "corei7-avx"] in {
def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures>; def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,
ProcessorFeatures.SNBTuning>;
} }
foreach P = ["ivybridge", "core-avx-i"] in { foreach P = ["ivybridge", "core-avx-i"] in {
def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures>; def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,
ProcessorFeatures.IVBTuning>;
} }
foreach P = ["haswell", "core-avx2"] in { foreach P = ["haswell", "core-avx2"] in {
def : ProcessorModel<P, HaswellModel, ProcessorFeatures.HSWFeatures>; def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,
ProcessorFeatures.HSWTuning>;
} }
def : ProcessorModel<"broadwell", BroadwellModel, def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures,
ProcessorFeatures.BDWFeatures>; ProcessorFeatures.BDWTuning>;
def : ProcessorModel<"skylake", SkylakeClientModel, def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,
ProcessorFeatures.SKLFeatures>; ProcessorFeatures.SKLTuning>;
// FIXME: define KNL scheduler model // FIXME: define KNL scheduler model
def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>; def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures,
def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>; ProcessorFeatures.KNLTuning>;
def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,
ProcessorFeatures.KNLTuning>;
foreach P = ["skylake-avx512", "skx"] in { foreach P = ["skylake-avx512", "skx"] in {
def : ProcessorModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures>; def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,
ProcessorFeatures.SKXTuning>;
} }
def : ProcessorModel<"cascadelake", SkylakeServerModel, def : ProcModel<"cascadelake", SkylakeServerModel,
ProcessorFeatures.CLXFeatures>; ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;
def : ProcessorModel<"cooperlake", SkylakeServerModel, def : ProcModel<"cooperlake", SkylakeServerModel,
ProcessorFeatures.CPXFeatures>; ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
def : ProcessorModel<"cannonlake", SkylakeServerModel, def : ProcModel<"cannonlake", SkylakeServerModel,
ProcessorFeatures.CNLFeatures>; ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
def : ProcessorModel<"icelake-client", SkylakeServerModel, def : ProcModel<"icelake-client", SkylakeServerModel,
ProcessorFeatures.ICLFeatures>; ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
def : ProcessorModel<"icelake-server", SkylakeServerModel, def : ProcModel<"icelake-server", SkylakeServerModel,
ProcessorFeatures.ICXFeatures>; ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
def : ProcessorModel<"tigerlake", SkylakeServerModel, def : ProcModel<"tigerlake", SkylakeServerModel,
ProcessorFeatures.TGLFeatures>; ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
// AMD CPUs. // AMD CPUs.
def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
FeatureMMX, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
Feature3DNow, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
Feature3DNow, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
foreach P = ["athlon", "athlon-tbird"] in { foreach P = ["athlon", "athlon-tbird"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA,
Feature3DNowA, FeatureNOPL, FeatureSlowSHLD, FeatureNOPL],
FeatureInsertVZEROUPPER]>; [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
} }
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
FeatureSlowSHLD, FeatureInsertVZEROUPPER]>; [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
} }
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA,
FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV],
Feature64Bit, FeatureSlowSHLD, FeatureCMOV, [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16,
FeatureFastScalarShiftMasks, FeatureInsertVZEROUPPER]>; FeatureInsertVZEROUPPER]>;
} }
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA,
Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV,
FeatureSlowSHLD, FeatureCMOV, Feature64Bit, Feature64Bit],
FeatureFastScalarShiftMasks, FeatureInsertVZEROUPPER]>; [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16,
FeatureInsertVZEROUPPER]>;
} }
foreach P = ["amdfam10", "barcelona"] in { foreach P = ["amdfam10", "barcelona"] in {
def : Proc<P, ProcessorFeatures.BarcelonaFeatures>; def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
ProcessorFeatures.BarcelonaTuning>;
} }
// Bobcat // Bobcat
def : Proc<"btver1", ProcessorFeatures.BtVer1Features>; def : Proc<"btver1", ProcessorFeatures.BtVer1Features,
ProcessorFeatures.BtVer1Tuning>;
// Jaguar // Jaguar
def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>; def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features,
ProcessorFeatures.BtVer2Tuning>;
// Bulldozer // Bulldozer
def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>; def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features,
ProcessorFeatures.BdVer1Tuning>;
// Piledriver // Piledriver
def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>; def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features,
ProcessorFeatures.BdVer2Tuning>;
// Steamroller // Steamroller
def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>; def : Proc<"bdver3", ProcessorFeatures.BdVer3Features,
ProcessorFeatures.BdVer3Tuning>;
// Excavator // Excavator
def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>; def : Proc<"bdver4", ProcessorFeatures.BdVer4Features,
ProcessorFeatures.BdVer4Tuning>;
def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
def : ProcessorModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features>;
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
Feature3DNowA, FeatureInsertVZEROUPPER]>; ProcessorFeatures.ZNTuning>;
def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, ProcessorFeatures.ZN2Tuning>;
FeatureInsertVZEROUPPER]>;
def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow, def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA],
FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow,
FeatureInsertVZEROUPPER]>; def : Proc<"winchip-c6", [FeatureX87, FeatureMMX],
def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
FeatureMMX, FeatureSSE1, FeatureFXSR, def : Proc<"winchip2", [FeatureX87, Feature3DNow],
FeatureCMOV, FeatureInsertVZEROUPPER]>; [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : Proc<"c3", [FeatureX87, Feature3DNow],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
FeatureSSE1, FeatureFXSR, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
// We also provide a generic 64-bit specific x86 processor model which tries to // We also provide a generic 64-bit specific x86 processor model which tries to
// be good for modern chips without enabling instruction set encodings past the // be good for modern chips without enabling instruction set encodings past the
// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
// modern 64-bit x86 chip, and enables features that are generally beneficial. // modern 64-bit x86 chip, and enables features that are generally beneficial.
// //
// We currently use the Sandy Bridge model as the default scheduling model as // We currently use the Sandy Bridge model as the default scheduling model as
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
// covers a huge swath of x86 processors. If there are specific scheduling // covers a huge swath of x86 processors. If there are specific scheduling
// knobs which need to be tuned differently for AMD chips, we might consider // knobs which need to be tuned differently for AMD chips, we might consider
// forming a common base for them. // forming a common base for them.
def : ProcessorModel<"x86-64", SandyBridgeModel, [ def : ProcModel<"x86-64", SandyBridgeModel, [
FeatureX87, FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSE2, FeatureSSE2,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
],
[
FeatureSlow3OpsLEA, FeatureSlow3OpsLEA,
FeatureSlowDivide64, FeatureSlowDivide64,
FeatureSlowIncDec, FeatureSlowIncDec,
FeatureMacroFusion, FeatureMacroFusion,
FeatureInsertVZEROUPPER FeatureInsertVZEROUPPER
]>; ]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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