[MLIR][SPIRVToLLVM] Conversion of GLSL ops to LLVM intrinsics

[georgemitenkov]

Summary

This patch introduces new intrinsics in LLVM dialect:

• llvm.intr.floor
• llvm.intr.maxnum
• llvm.intr.minnum
• llvm.intr.smax
• llvm.intr.smin

These intrinsics correspond to SPIR-V ops from GLSL
extended instruction set (spv.GLSL.Floor, spv.GLSL.FMax,
spv.GLSL.FMin, spv.GLSL.SMax and spv.GLSL.SMin
respectively). Also conversion patterns for them were added.

[georgemitenkov]

Also added other intrinsics to this patch since they fall in the same category:

• SMin
• SMax
• FMin (minnum in LLVM)
• FMax (maxnum in LLVM)

[ftynse]

mlir/test/Target/llvmir-intrinsics.mlir

149

https://github.com/llvm/llvm-project/commit/647e9a54c758a6fdd85a569f019f00a653b2bc40#diff-0b1def52ecd98fbfee0db808b498a6ec makes me think the leading whitespace is tabs. Please use spaces rather than tabs in tests and elsewhere, https://llvm.org/docs/CodingStandards.html#whitespace.

[georgemitenkov]

mlir/test/Target/llvmir-intrinsics.mlir

149

Thanks for pointing that out! Will address in a separate patch, I think it is actually a reoccurring issue in all the tests.

mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td

class LLVM_TernarySameArgsIntrinsicOp<string func, list<OpTrait> traits = []> :
     Arguments<(ins LLVM_Type:$a, LLVM_Type:$b, LLVM_Type:$c)>;
 
 def LLVM_CopySignOp : LLVM_BinarySameArgsIntrinsicOp<"copysign">;
 def LLVM_CosOp : LLVM_UnaryIntrinsicOp<"cos">;
 def LLVM_ExpOp : LLVM_UnaryIntrinsicOp<"exp">;
 def LLVM_Exp2Op : LLVM_UnaryIntrinsicOp<"exp2">;
 def LLVM_FAbsOp : LLVM_UnaryIntrinsicOp<"fabs">;
 def LLVM_FCeilOp : LLVM_UnaryIntrinsicOp<"ceil">;
+def LLVM_FFloorOp : LLVM_UnaryIntrinsicOp<"floor">;
 def LLVM_FMAOp : LLVM_TernarySameArgsIntrinsicOp<"fma">;
 def LLVM_FMulAddOp : LLVM_TernarySameArgsIntrinsicOp<"fmuladd">;
 def LLVM_Log10Op : LLVM_UnaryIntrinsicOp<"log10">;
 def LLVM_Log2Op : LLVM_UnaryIntrinsicOp<"log2">;
 def LLVM_LogOp : LLVM_UnaryIntrinsicOp<"log">;
 def LLVM_Prefetch : LLVM_ZeroResultIntrOp<"prefetch", [0]>,
                     Arguments<(ins LLVM_Type:$addr, LLVM_Type:$rw,
                                LLVM_Type:$hint, LLVM_Type:$cache)>;

mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp

patterns.insert<
       // Function Call op
       FunctionCallPattern,
 
       // GLSL extended instruction set ops
       DirectConversionPattern<spirv::GLSLCeilOp, LLVM::FCeilOp>,
       DirectConversionPattern<spirv::GLSLCosOp, LLVM::CosOp>,
       DirectConversionPattern<spirv::GLSLExpOp, LLVM::ExpOp>,
       DirectConversionPattern<spirv::GLSLFAbsOp, LLVM::FAbsOp>,
+      DirectConversionPattern<spirv::GLSLFloorOp, LLVM::FFloorOp>,
       DirectConversionPattern<spirv::GLSLLogOp, LLVM::LogOp>,
       DirectConversionPattern<spirv::GLSLSinOp, LLVM::SinOp>,
       DirectConversionPattern<spirv::GLSLSqrtOp, LLVM::SqrtOp>,
       InverseSqrtPattern, TanPattern, TanhPattern,
 
       // Logical ops
       DirectConversionPattern<spirv::LogicalAndOp, LLVM::AndOp>,
       DirectConversionPattern<spirv::LogicalOrOp, LLVM::OrOp>,

mlir/test/Conversion/SPIRVToLLVM/glsl-ops-to-llvm.mlir

func @fabs(%arg0: f32, %arg1: vector<3xf16>) {
   // CHECK: %{{.*}} = "llvm.intr.fabs"(%{{.*}}) : (!llvm.float) -> !llvm.float
   %0 = spv.GLSL.FAbs %arg0 : f32
   // CHECK: %{{.*}} = "llvm.intr.fabs"(%{{.*}}) : (!llvm<"<3 x half>">) -> !llvm<"<3 x half>">
   %1 = spv.GLSL.FAbs %arg1 : vector<3xf16>
   return
 }
 
 //===----------------------------------------------------------------------===//
+// spv.GLSL.Floor
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @floor
+func @floor(%arg0: f32, %arg1: vector<3xf16>) {
+  // CHECK: "llvm.intr.floor"(%{{.*}}) : (!llvm.float) -> !llvm.float
+  %0 = spv.GLSL.Floor %arg0 : f32
+  // CHECK: "llvm.intr.floor"(%{{.*}}) : (!llvm<"<3 x half>">) -> !llvm<"<3 x half>">
+  %1 = spv.GLSL.Floor %arg1 : vector<3xf16>
+  return
+}
+
+//===----------------------------------------------------------------------===//
 // spv.GLSL.Log
 //===----------------------------------------------------------------------===//
 
 func @log(%arg0: f32, %arg1: vector<3xf16>) {
   // CHECK: %{{.*}} = "llvm.intr.log"(%{{.*}}) : (!llvm.float) -> !llvm.float
   %0 = spv.GLSL.Log %arg0 : f32
   // CHECK: %{{.*}} = "llvm.intr.log"(%{{.*}}) : (!llvm<"<3 x half>">) -> !llvm<"<3 x half>">
   %1 = spv.GLSL.Log %arg1 : vector<3xf16>

mlir/test/Target/llvmir-intrinsics.mlir

 llvm.func @ceil_test(%arg0: !llvm.float, %arg1: !llvm<"<8 x float>">) {
   // CHECK: call float @llvm.ceil.f32
   "llvm.intr.ceil"(%arg0) : (!llvm.float) -> !llvm.float
   // CHECK: call <8 x float> @llvm.ceil.v8f32
   "llvm.intr.ceil"(%arg1) : (!llvm<"<8 x float>">) -> !llvm<"<8 x float>">
   llvm.return
 }
 
+// CHECK-LABEL: @floor_test
+llvm.func @floor_test(%arg0: !llvm.float, %arg1: !llvm<"<8 x float>">) {
+  // CHECK: call float @llvm.floor.f32
+  "llvm.intr.floor"(%arg0) : (!llvm.float) -> !llvm.float
+  // CHECK: call <8 x float> @llvm.floor.v8f32
+  "llvm.intr.floor"(%arg1) : (!llvm<"<8 x float>">) -> !llvm<"<8 x float>">
+  llvm.return
+}
+
 // CHECK-LABEL: @cos_test
 llvm.func @cos_test(%arg0: !llvm.float, %arg1: !llvm<"<8 x float>">) {
   // CHECK: call float @llvm.cos.f32
   "llvm.intr.cos"(%arg0) : (!llvm.float) -> !llvm.float
   // CHECK: call <8 x float> @llvm.cos.v8f32
   "llvm.intr.cos"(%arg1) : (!llvm<"<8 x float>">) -> !llvm<"<8 x float>">
   llvm.return
 }
llvm.func @ctpop_test(%arg0: !llvm.i32, %arg1: !llvm<"<8 x i32>">) {
   "llvm.intr.ctpop"(%arg0) : (!llvm.i32) -> !llvm.i32
   // CHECK: call <8 x i32> @llvm.ctpop.v8i32
   "llvm.intr.ctpop"(%arg1) : (!llvm<"<8 x i32>">) -> !llvm<"<8 x i32>">
   llvm.return
 }
 
 // CHECK-LABEL: @vector_reductions
 llvm.func @vector_reductions(%arg0: !llvm.float, %arg1: !llvm<"<8 x float>">, %arg2: !llvm<"<8 x i32>">) {
   // CHECK: call i32 @llvm.experimental.vector.reduce.add.v8i32
   "llvm.intr.experimental.vector.reduce.add"(%arg2) : (!llvm<"<8 x i32>">) -> !llvm.i32
   // CHECK: call i32 @llvm.experimental.vector.reduce.and.v8i32
   "llvm.intr.experimental.vector.reduce.and"(%arg2) : (!llvm<"<8 x i32>">) -> !llvm.i32
   // CHECK: call float @llvm.experimental.vector.reduce.fmax.v8f32
   "llvm.intr.experimental.vector.reduce.fmax"(%arg1) : (!llvm<"<8 x float>">) -> !llvm.float
   // CHECK: call float @llvm.experimental.vector.reduce.fmin.v8f32
   "llvm.intr.experimental.vector.reduce.fmin"(%arg1) : (!llvm<"<8 x float>">) -> !llvm.float
   // CHECK: call i32 @llvm.experimental.vector.reduce.mul.v8i32