[MLIR][Affine] Add test for non-hyperrectangular loop tiling

[kumasento]

Summary

This diff provides a concrete test case for the error that will be raised when the iteration space is non hyper-rectangular.

The corresponding emission method for this error message has been changed as well.

[kumasento]

Reverted the accidental change in loop-tiling.mlir

[bondhugula]

Thanks very much for improving this.

mlir/test/Dialect/Affine/loop-tiling-invalid.mlir

2

You won't need -allow-unregistered-dialect.

2

This file can be named loop-tiling-unsupported.mlir. There's nothing invalid here.

16

Missing line break at the end.

[kumasento]

Fixed issues about cmd, file naming, and missing NL.

[kumasento]

Thank you very much @bondhugula for your comments! I've updated this diff accordingly :)

[bondhugula]

Thanks!

[bondhugula]

Let me know if you'd like me to commit this for you.

[kumasento]

In D84531#2174290, @bondhugula wrote:

Let me know if you'd like me to commit this for you.

Hi @bondhugula Thanks! That would be great :)

[bondhugula]

mlir/test/Dialect/Affine/loop-tiling-unsupported.mlir

3 ↗

(On Diff #280526)

You don't have a -split-input-file as an option but you have this splitter. I'll fix this before committing.

mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp

mlir::tilePerfectlyNested(MutableArrayRef<AffineForOp> input,
   moveLoopBody(origLoops.back(), innermostPointLoop);
 
   SmallVector<Value, 8> origLoopIVs;
   extractForInductionVars(input, &origLoopIVs);
 
   FlatAffineConstraints cst;
   getIndexSet(input, &cst);
   if (!cst.isHyperRectangular(0, width)) {
-    llvm::dbgs() << "tiled code generation unimplemented for the "
-                    "non-hyperrectangular case, op:"
-                 << *rootAffineForOp << "\n";
+    rootAffineForOp.emitError("tiled code generation unimplemented for the "
+                              "non-hyperrectangular case");
     return failure();
   }
 
   constructTiledIndexSetHyperRect(origLoops, tiledLoops, tileSizes);
 
   // Replace original IVs with intra-tile loop IVs.
   for (unsigned i = 0; i < width; i++)
     origLoopIVs[i].replaceAllUsesWith(tiledLoops[i + width].getInductionVar());

mlir/test/Dialect/Affine/loop-tiling-invalid.mlir

+// RUN: mlir-opt -allow-unregistered-dialect %s -verify-diagnostics -affine-loop-tile="tile-size=32"
+
+// -----
+
+#ub = affine_map<(d0)[s0] -> (d0, s0)>
+func @non_hyperrect_loop() {
+  %N = constant 128 : index
+  // expected-error@+1 {{tiled code generation unimplemented for the non-hyperrectangular case}}
+  affine.for %i = 0 to %N {
+    affine.for %j = 0 to min #ub(%i)[%N] {
+      affine.yield
+    }
+  }
+  return 
+}
 No newline at end of file

mlir/test/Dialect/Affine/loop-tiling.mlir

-// RUN: mlir-opt %s -split-input-file -affine-loop-tile="tile-size=32" | FileCheck %s
+// RUN: mlir-opt %s -split-input-file -affine-loop-tile="tile-size=32" -verify-diagnostics | FileCheck %s
 // RUN: mlir-opt %s -split-input-file -affine-loop-tile="cache-size=512" | FileCheck %s --check-prefix=MODEL
 // RUN: mlir-opt %s -split-input-file -affine-loop-tile="tile-size=32 separate" | FileCheck %s --check-prefix=SEPARATE
 
 // -----
 
 // CHECK-DAG: [[$UB:#map[0-9]+]] = affine_map<(d0) -> (d0 + 32)>
 // CHECK-DAG: [[$UB_MIN:#map[0-9]+]] = affine_map<(d0) -> (d0 + 32, 50)>
 // CHECK-DAG: [[$ID:#map[0-9]+]] = affine_map<(d0) -> (d0)>