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Differential D84382

[PowerPC][Power10] Cleanup p10vector clang test
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Authored by biplmish on Jul 22 2020, 9:06 PM.

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Reviewers
nemanjai
amyk
lei
Group Reviewers
Restricted Project
Commits
rG0eff8b3865ed: [PowerPC] Cleanup p10vector clang test
Summary

This patch removes the duplicate LE test, corrects the labels and removes common tests for vec_splat builtin.

Diff Detail

Event Timeline

biplmish created this revision.Jul 22 2020, 9:06 PM
Herald added subscribers: shchenz, • wuzish, kbarton. · View Herald TranscriptJul 22 2020, 9:06 PM
biplmish set the repository for this revision to rG LLVM Github Monorepo.Jul 23 2020, 4:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 23 2020, 4:43 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
lei accepted this revision.Jul 23 2020, 5:34 AM

LGTM
thx!

This revision is now accepted and ready to land.Jul 23 2020, 5:34 AM
amyk accepted this revision.Jul 23 2020, 6:56 AM

LGTM as well.

Closed by commit rG0eff8b3865ed: [PowerPC] Cleanup p10vector clang test (authored by biplmish). · Explain WhyJul 26 2020, 7:23 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
test/
CodeGen/
53 lines

Diff 280769

clang/test/CodeGen/builtins-ppc-p10vector.c

// REQUIRES: powerpc-registered-target // REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \ // RUN: %clang_cc1 -target-feature +vsx \
// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s
// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
// RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK
// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \ // RUN: %clang_cc1 -target-feature +vsx \
// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK
#include <altivec.h> #include <altivec.h>
vector signed char vsca, vscb; vector signed char vsca, vscb;
vector unsigned char vuca, vucb, vucc; vector unsigned char vuca, vucb, vucc;
vector signed short vssa, vssb; vector signed short vssa, vssb;
vector unsigned short vusa, vusb, vusc; vector unsigned short vusa, vusb, vusc;
vector signed int vsia, vsib; vector signed int vsia, vsib;
▲ Show 20 Lines • Show All 488 Lines • ▼ Show 20 Linesvector unsigned int test_vec_inserth_uiv(void) {
// CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32>
// CHECK-BE-NEXT: ret <4 x i32> // CHECK-BE-NEXT: ret <4 x i32>
// CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32>
// CHECK-LE-NEXT: ret <4 x i32> // CHECK-LE-NEXT: ret <4 x i32>
return vec_inserth(vuia, vuib, uia); return vec_inserth(vuia, vuib, uia);
} }
vector signed int test_vec_vec_splati_si(void) { vector signed int test_vec_vec_splati_si(void) {
// CHECK-BE: ret <4 x i32> <i32 -17, i32 -17, i32 -17, i32 -17>
// CHECK: ret <4 x i32> <i32 -17, i32 -17, i32 -17, i32 -17> // CHECK: ret <4 x i32> <i32 -17, i32 -17, i32 -17, i32 -17>
return vec_splati(-17); return vec_splati(-17);
} }
vector unsigned int test_vec_vec_splati_ui(void) { vector unsigned int test_vec_vec_splati_ui(void) {
// CHECK-BE: ret <4 x i32> <i32 16, i32 16, i32 16, i32 16>
// CHECK: ret <4 x i32> <i32 16, i32 16, i32 16, i32 16> // CHECK: ret <4 x i32> <i32 16, i32 16, i32 16, i32 16>
return vec_splati(16U); return vec_splati(16U);
} }
vector float test_vec_vec_splati_f(void) { vector float test_vec_vec_splati_f(void) {
// CHECK-BE: ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
// CHECK: ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> // CHECK: ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
return vec_splati(1.0f); return vec_splati(1.0f);
} }
vector double test_vec_vec_splatid(void) { vector double test_vec_vec_splatid(void) {
// CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double // CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double
// CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0 // CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0
// CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize // CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize
// CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]] // CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]]
// CHECK: [[T1:%.+]] = fpext float %{{.+}} to double // CHECK-LE: [[T1:%.+]] = fpext float %{{.+}} to double
// CHECK-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0 // CHECK-LE-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double [[T1:%.+]], i32 0
// CHECK-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize // CHECK-LE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x double> undef, <2 x i32> zeroinitialize
// CHECK-NEXT: ret <2 x double> [[T3:%.+]] // CHECK-LE-NEXT: ret <2 x double> [[T3:%.+]]
return vec_splatid(1.0); return vec_splatid(1.0);
} }
vector signed int test_vec_vec_splati_ins_si(void) { vector signed int test_vec_vec_splati_ins_si(void) {
// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
// CHECK-BE: ret <4 x i32> // CHECK-BE: ret <4 x i32>
// CHECK: [[T1:%.+]] = sub i32 1, %{{.+}} // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}}
// CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
// CHECK: [[T2:%.+]] = sub i32 3, %{{.+}} // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}}
// CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
// CHECK: ret <4 x i32> // CHECK-LE: ret <4 x i32>
return vec_splati_ins(vsia, 0, -17); return vec_splati_ins(vsia, 0, -17);
} }
vector unsigned int test_vec_vec_splati_ins_ui(void) { vector unsigned int test_vec_vec_splati_ins_ui(void) {
// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}} // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
// CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
// CHECK-BE: ret <4 x i32> // CHECK-BE: ret <4 x i32>
// CHECK: [[T1:%.+]] = sub i32 1, %{{.+}} // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}}
// CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]] // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
// CHECK: [[T2:%.+]] = sub i32 3, %{{.+}} // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}}
// CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]] // CHECK-LE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T2]]
// CHECK: ret <4 x i32> // CHECK-LE: ret <4 x i32>
return vec_splati_ins(vuia, 1, 16U); return vec_splati_ins(vuia, 1, 16U);
} }
vector float test_vec_vec_splati_ins_f(void) { vector float test_vec_vec_splati_ins_f(void) {
// CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}} // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 %{{.+}}
// CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}} // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
// CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]] // CHECK-BE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
// CHECK-BE: ret <4 x float> // CHECK-BE: ret <4 x float>
// CHECK: [[T1:%.+]] = sub i32 1, %{{.+}} // CHECK-LE: [[T1:%.+]] = sub i32 1, %{{.+}}
// CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]] // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
// CHECK: [[T2:%.+]] = sub i32 3, %{{.+}} // CHECK-LE: [[T2:%.+]] = sub i32 3, %{{.+}}
// CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]] // CHECK-LE: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]]
// CHECK: ret <4 x float> // CHECK-LE: ret <4 x float>
return vec_splati_ins(vfa, 0, 1.0f); return vec_splati_ins(vfa, 0, 1.0f);
} }
void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b, void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
signed char *__c) { signed char *__c) {
// CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1 // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
vec_xst_trunc(__a, __b, __c); vec_xst_trunc(__a, __b, __c);
} }
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines