Scheduler will try to retrieve the offset and base addr to determine if two loads/stores are disjoint memory access. PowerPC failed to handle this for frame index which will bring extra memory dependency for loads/stores. See.
SU(15): STW %7:gprc, 28, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 28)
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 1
Height : 7
Predecessors:
SU(0): Data Latency=1 Reg=%7
Successors:
SU(17): Ord Latency=1 Memory
SU(16): Ord Latency=1 Memory
Pressure Diff : GPRC 1 SPILLTOVSRRC 1 SPILLTOVSRRC_with_VFRC 1 F4RC_with_SPILLTOVSRRC 1 VSSRC_with_SPILLTOVSRRC 1
Single Issue : false;
SU(16): %8:gprc = LWZ 84, %fixed-stack.0 :: (dereferenceable load 4 from %ir.arrayidx_b + 4, align 8)
# preds left : 8
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 2
Height : 6
Predecessors:
SU(15): Ord Latency=1 Memory #<--- Extra dependency which is not needed.
SU(14): Ord Latency=1 Memory
SU(13): Ord Latency=1 Memory
SU(12): Ord Latency=1 Memory
SU(11): Ord Latency=1 Memory
SU(10): Ord Latency=1 Memory
SU(9): Ord Latency=1 Memory
SU(8): Ord Latency=1 Memory
Nit: this shouldn't be DAG -- STW 20 should be before others because of following overlapped LBZ.