[SVE] Fix invalid assert in expand_DestructiveOp.

[paulwalker-arm]

Summary

AArch64ExpandPseudo::expand_DestructiveOp contains an assert to
ensure the destructive operand's register is unique. However,
this is only required when psuedo expansion emits a movprfx.

A simple example when a movprfx is not required is

Z0 = FADD_ZPZZ_UNDEF_S P0, Z0, Z0

which expands to an unprefixed FADD_ZPmZ_S instruction.

This patch moves the assert to the places where a movprfx is emitted.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

481

Why are you wrapping this in #ifndef NDEBUG ?

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

481

The definition of DOPRegIsUnique is protected by NDEBUG.

[sdesmalen]

LGTM

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

481

Okay that makes sense, thanks.

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

case AArch64::DestructiveBinaryCommWithRev:
     DOPRegIsUnique =
       DstReg != MI.getOperand(DOPIdx).getReg() ||
       MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg();
     break;
   case AArch64::DestructiveBinaryImm:
     DOPRegIsUnique = true;
     break;
   }
-
-  assert (DOPRegIsUnique && "The destructive operand should be unique");
 #endif
 
   // Resolve the reverse opcode
   if (UseRev) {
     if (AArch64::getSVERevInstr(Opcode) != -1)
       Opcode = AArch64::getSVERevInstr(Opcode);
     else if (AArch64::getSVEOrigInstr(Opcode) != -1)
       Opcode = AArch64::getSVEOrigInstr(Opcode);
default:
     llvm_unreachable("Unsupported ElementSize");
   }
 
   //
   // Create the destructive operation (if required)
   //
   MachineInstrBuilder PRFX, DOP;
   if (FalseZero) {
+#ifndef NDEBUG
+    assert(DOPRegIsUnique && "The destructive operand should be unique");
+#endif
     assert(ElementSize != AArch64::ElementSizeNone &&
            "This instruction is unpredicated");
 
     // Merge source operand into destination register
     PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfxZero))
                .addReg(DstReg, RegState::Define)
                .addReg(MI.getOperand(PredIdx).getReg())
                .addReg(MI.getOperand(DOPIdx).getReg());
 
     // After the movprfx, the destructive operand is same as Dst
     DOPIdx = 0;
   } else if (DstReg != MI.getOperand(DOPIdx).getReg()) {
+#ifndef NDEBUG
+    assert(DOPRegIsUnique && "The destructive operand should be unique");
+#endif
     PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfx))
                .addReg(DstReg, RegState::Define)
                .addReg(MI.getOperand(DOPIdx).getReg());
     DOPIdx = 0;
   }
 
   //
   // Create the destructive operation

llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir

+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=aarch64-expand-pseudo -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+---
+name:            add_x
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$p0' }
+  - { reg: '$z0' }
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: $p0, $z0
+
+    ; CHECK: add_x
+    ; CHECK-NOT: MOVPRFX
+    ; CHECK: $z0 = FADD_ZPmZ_S renamable $p0, killed $z0, renamable $z0
+    ; CHECK-NEXT: RET
+    renamable $z0 = FADD_ZPZZ_UNDEF_S renamable $p0, renamable $z0, killed renamable $z0
+    RET_ReallyLR
+
+...