[X86] Replace (v)palignr intrinsics with generic shuffles (LLVM)
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Authored by RKSimon on Mar 12 2015, 10:50 AM.

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Summary

The (v)palignr instructions are currently described using builtin intrinsics although the x86 shuffle lowering code now correctly identifies them.

This patch auto upgrades the palignr builtins to generic shuffles. I was also able to enable an old broken test (palign-2.ll).

Companion patch to D8301

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RKSimon retitled this revision from to [X86] Replace (v)palignr intrinsics with generic shuffles (LLVM).Mar 12 2015, 10:50 AM
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I don't see those intrinsics in the IntrinsicsX86.td file. How does that test even work today?

I don't see those intrinsics in the IntrinsicsX86.td file. How does that test even work today?

From what I can tell it hasn't ever worked properly - if you look at the history of the test file the palignr has never been actually CHECK'd for - just the CHECK-LABEL and in reality the compiled function was making a call....

The old lowering code did an OK job at detecting palignr from shuffles - although it didn't take into account the zeroing for imm > lanesize

I'd be quite happy for this patch just to become a delete of palign-2.ll if everyone else agrees.

I'd rather just delete the test than emulate intrinsics that haven't been supported in a very long time. I'm not even sure if the AVX2 one ever existed.

RKSimon updated this revision to Diff 21861.Mar 12 2015, 11:44 AM

That's fine by me - updated patch, such as it is ;-)

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