[X86] Replace (v)palignr intrinsics with generic shuffles (LLVM)

[RKSimon]

Summary

The (v)palignr instructions are currently described using builtin intrinsics although the x86 shuffle lowering code now correctly identifies them.

This patch auto upgrades the palignr builtins to generic shuffles. I was also able to enable an old broken test (palign-2.ll).

Companion patch to D8301

[craig.topper]

I don't see those intrinsics in the IntrinsicsX86.td file. How does that test even work today?

[RKSimon]

In D8302#139996, @craig.topper wrote:

I don't see those intrinsics in the IntrinsicsX86.td file. How does that test even work today?

From what I can tell it hasn't ever worked properly - if you look at the history of the test file the palignr has never been actually CHECK'd for - just the CHECK-LABEL and in reality the compiled function was making a call....

The old lowering code did an OK job at detecting palignr from shuffles - although it didn't take into account the zeroing for imm > lanesize

I'd be quite happy for this patch just to become a delete of palign-2.ll if everyone else agrees.

[craig.topper]

I'd rather just delete the test than emulate intrinsics that haven't been supported in a very long time. I'm not even sure if the AVX2 one ever existed.

[RKSimon]

That's fine by me - updated patch, such as it is ;-)

llvm/trunk/test/CodeGen/X86/palignr-2.ll

-; RUN: llc < %s -march=x86 -mattr=+ssse3 | FileCheck %s
-; rdar://7341330
-
-@a = global [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 16 ; <[4 x i32]*> [#uses=1]
-@c = common global [4 x i32] zeroinitializer, align 16 ; <[4 x i32]*> [#uses=1]
-@b = global [4 x i32] [i32 0, i32 1, i32 2, i32 3], align 16 ; <[4 x i32]*> [#uses=1]
-
-define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; palignr $3, %xmm1, %xmm0
-  %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
-  store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
-  ret void
-}
-
-declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
-
-define void @t2() nounwind ssp {
-entry:
-; CHECK-LABEL: t2:
-; palignr $4, _b, %xmm0
-  %0 = load <2 x i64>, <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
-  %1 = load <2 x i64>, <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
-  %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone
-  store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
-  ret void
-}