MIR: Infer not-SSA for subregister defs

[arsenm]

Summary

It's possible to have a single virtual register def with a subreg
index that would pass the previous check, but it's not possible to
have a subregister def in SSA.

This is in preparation for adding stricter checks for SSA MIR.

[thegameg]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

453

There is a MachineInstr *getUniqueVRegDef(Register Reg) const;. Maybe name this one getUniqueVRegDefOperand? Are they actually vreg-only?

[arsenm]

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

453

I guess this would technically work for physical registers. I picked the name to mirror the existing hasOneDef just above

[arsenm]

ping

[arsenm]

ping

[arsenm]

ping

[qcolombet]

LGTM

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

330

Replying to the FIXME: Unclear, if Reg is a reserved reg, maybe that's fine.
I could also be that we removed the implicit_defs.

[arsenm]

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

330

I was working on making it illegal to remove implicit_defs in ssa at the time I did this; however the complication is implicit_defs are folded into undef operands just before phi elimination so we end up in a weird half-SSA state

[arsenm]

ee679638d75ca9a7f7d7be728fa069606dcc8ec7

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

public:
   /// register.
   bool hasOneDef(Register RegNo) const {
     def_iterator DI = def_begin(RegNo);
     if (DI == def_end())
       return false;
     return ++DI == def_end();
   }
 
+  /// Returns the defining operand if there is exactly one operand defining the
+  /// specified register, otherwise nullptr.
+  MachineOperand *getOneDef(Register Reg) const {
+    def_iterator DI = def_begin(Reg);
+    if (DI == def_end()) // No defs.
+      return nullptr;
+
+    def_iterator OneDef = DI;
+    if (++DI == def_end())
+      return &*OneDef;
+    return nullptr; // Multiple defs.
+  }
+
   /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
   using use_iterator =
       defusechain_iterator<true, false, false, true, false, false>;
   use_iterator use_begin(Register RegNo) const {
     return use_iterator(getRegUseDefListHead(RegNo));
   }
   static use_iterator use_end() { return use_iterator(nullptr); }
 

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

if (initializeMachineFunction(YamlMF, MF))
     return true;
 
   return false;
 }
 
 static bool isSSA(const MachineFunction &MF) {
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
-    unsigned Reg = Register::index2VirtReg(I);
+    Register Reg = Register::index2VirtReg(I);
     if (!MRI.hasOneDef(Reg) && !MRI.def_empty(Reg))
       return false;
+
+    // FIXME: def_empty should count as an SSA violation.
+    // Subregister defs are invalid in SSA.
+    const MachineOperand *RegDef = MRI.getOneDef(Reg);
+    if (RegDef && RegDef->getSubReg() != 0)
+      return false;
   }
   return true;
 }
 
 void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
   MachineFunctionProperties &Properties = MF.getProperties();
 
   bool HasPHI = false;

llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir

+# REQUIRES: asserts
+# RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
+
+# CHECK: MachineFunctionProperties required by InstructionSelect pass are not met by function subreg_def_is_not_ssa.
+# CHECK-NEXT: Required properties: IsSSA
+# CHECK-NEXT: Current properties: NoPHIs
+# CHECK-NEXT: MachineFunctionProperties check failed
+
+---
+name: subreg_def_is_not_ssa
+
+body: |
+  bb.0:
+    %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+
+...