[MLIR][SPIRVToLLVM] Implementation of bitwise and logical not

[georgemitenkov]

Summary

This patch introduces new conversion patterns for bit and logical negation op: spv.Not and spv.LogicalNot. They are implemented by applying xor on the operand and mask with all bits set.

[georgemitenkov]

• [MLIR][SPIRVToLLVM] Removed commented out code

Removed the code for commented out pattern.

[ftynse]

LGTM after addressing the comments

mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp

56

Nit: please put a full stop at the end of each sentence. (https://llvm.org/docs/CodingStandards.html#commenting)

187

Is this cast necessary? AFAIR, VectorType derives from ShapedType

[georgemitenkov]

• [MLIR][SPIRVToLLVM] Addressed comments on NotPattern conversion class

Added a full stop at the end of each sentence. When creating a vector constant with all bits set, cast of srcType to VectorType is used instead of ShapedType. The cast is necessary for type checks.

mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp

if (type.isIntOrFloat())
     return type.getIntOrFloatBitWidth();
   auto vecType = type.dyn_cast<VectorType>();
   auto elementType = vecType.getElementType();
   assert(elementType.isIntOrFloat() &&
          "only integers and floats have a bitwidth");
   return elementType.getIntOrFloatBitWidth();
 }
 
+/// Creates `IntegerAttribute` with all bits set for given type
+IntegerAttr minusOneIntegerAttribute(Type type, Builder builder) {
+  if (auto vecType = type.dyn_cast<VectorType>()) {
+    auto integerType = vecType.getElementType().cast<IntegerType>();
+    return builder.getIntegerAttr(integerType, -1);
+  }
+  auto integerType = type.cast<IntegerType>();
+  return builder.getIntegerAttr(integerType, -1);
+}
+
 //===----------------------------------------------------------------------===//
 // Operation conversion
 //===----------------------------------------------------------------------===//
 
 namespace {
 
 /// Converts SPIR-V operations that have straightforward LLVM equivalent
 /// into LLVM dialect operations.
matchAndRewrite(SPIRVOp operation, ArrayRef<Value> operands,
     rewriter.template replaceOpWithNewOp<LLVM::ICmpOp>(
         operation, dstType,
         rewriter.getI64IntegerAttr(static_cast<int64_t>(predicate)),
         operation.operand1(), operation.operand2());
     return success();
   }
 };
 
+/// Converts `spv.Not` and `spv.LogicalNot` into LLVM dialect
+template <typename SPIRVOp>
+class NotPattern : public SPIRVToLLVMConversion<SPIRVOp> {
+public:
+  using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
+
+  LogicalResult
+  matchAndRewrite(SPIRVOp notOp, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const override {
+
+    auto srcType = notOp.getType();
+    auto dstType = this->typeConverter.convertType(srcType);
+    if (!dstType)
+      return failure();
+
+    Location loc = notOp.getLoc();
+    IntegerAttr minusOne = minusOneIntegerAttribute(srcType, rewriter);
+    auto mask = srcType.template isa<VectorType>()
+                    ? rewriter.create<LLVM::ConstantOp>(
+                          loc, dstType,
+                          SplatElementsAttr::get(
+                              srcType.template cast<ShapedType>(), minusOne))
+                    : rewriter.create<LLVM::ConstantOp>(loc, dstType, minusOne);
+    rewriter.template replaceOpWithNewOp<LLVM::XOrOp>(notOp, dstType,
+                                                      notOp.operand(), mask);
+    return success();
+  }
+};
+
 class ReturnPattern : public SPIRVToLLVMConversion<spirv::ReturnOp> {
 public:
   using SPIRVToLLVMConversion<spirv::ReturnOp>::SPIRVToLLVMConversion;
 
   LogicalResult
   matchAndRewrite(spirv::ReturnOp returnOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(returnOp, ArrayRef<Type>(),
patterns.insert<
       DirectConversionPattern<spirv::SRemOp, LLVM::SRemOp>,
       DirectConversionPattern<spirv::UDivOp, LLVM::UDivOp>,
       DirectConversionPattern<spirv::UModOp, LLVM::URemOp>,
 
       // Bitwise ops
       DirectConversionPattern<spirv::BitwiseAndOp, LLVM::AndOp>,
       DirectConversionPattern<spirv::BitwiseOrOp, LLVM::OrOp>,
       DirectConversionPattern<spirv::BitwiseXorOp, LLVM::XOrOp>,
+      NotPattern<spirv::NotOp>,
 
       // Cast ops
       DirectConversionPattern<spirv::ConvertFToSOp, LLVM::FPToSIOp>,
       DirectConversionPattern<spirv::ConvertFToUOp, LLVM::FPToUIOp>,
       DirectConversionPattern<spirv::ConvertSToFOp, LLVM::SIToFPOp>,
       DirectConversionPattern<spirv::ConvertUToFOp, LLVM::UIToFPOp>,
       IndirectCastPattern<spirv::FConvertOp, LLVM::FPExtOp, LLVM::FPTruncOp>,
       IndirectCastPattern<spirv::SConvertOp, LLVM::SExtOp, LLVM::TruncOp>,
patterns.insert<
       IComparePattern<spirv::ULessThanEqualOp, LLVM::ICmpPredicate::ule>,
       IComparePattern<spirv::ULessThanOp, LLVM::ICmpPredicate::ult>,
 
       // Logical ops
       DirectConversionPattern<spirv::LogicalAndOp, LLVM::AndOp>,
       DirectConversionPattern<spirv::LogicalOrOp, LLVM::OrOp>,
       IComparePattern<spirv::LogicalEqualOp, LLVM::ICmpPredicate::eq>,
       IComparePattern<spirv::LogicalNotEqualOp, LLVM::ICmpPredicate::ne>,
+      NotPattern<spirv::LogicalNotOp>,
 
       // Shift ops
       ShiftPattern<spirv::ShiftRightArithmeticOp, LLVM::AShrOp>,
       ShiftPattern<spirv::ShiftRightLogicalOp, LLVM::LShrOp>,
       ShiftPattern<spirv::ShiftLeftLogicalOp, LLVM::ShlOp>,
 
       // Return ops
       ReturnPattern, ReturnValuePattern>(context, typeConverter);

mlir/test/Conversion/SPIRVToLLVM/bitwise-ops-to-llvm.mlir

func @bitwise_xor_scalar(%arg0: i32, %arg1: i32) {
   return
 }
 
 func @bitwise_xor_vector(%arg0: vector<2xi16>, %arg1: vector<2xi16>) {
   // CHECK: %{{.*}} = llvm.xor %{{.*}}, %{{.*}} : !llvm<"<2 x i16>">
   %0 = spv.BitwiseXor %arg0, %arg1 : vector<2xi16>
   return
 }
+
+//===----------------------------------------------------------------------===//
+// spv.Not
+//===----------------------------------------------------------------------===//
+
+func @not__scalar(%arg0: i32) {
+  // CHECK: %[[CONST:.*]] = llvm.mlir.constant(-1 : i32) : !llvm.i32
+  // CHECK: %{{.*}} = llvm.xor %{{.*}}, %[[CONST]] : !llvm.i32
+  %0 = spv.Not %arg0 : i32
+  return
+}
+
+func @not_vector(%arg0: vector<2xi16>) {
+  // CHECK: %[[CONST:.*]] = llvm.mlir.constant(dense<-1> : vector<2xi16>) : !llvm<"<2 x i16>">
+  // CHECK: %{{.*}} = llvm.xor %{{.*}}, %[[CONST]] : !llvm<"<2 x i16>">
+  %0 = spv.Not %arg0 : vector<2xi16>
+  return
+}

mlir/test/Conversion/SPIRVToLLVM/logical-to-llvm.mlir

 
 func @logical_not_equal_vector(%arg0: vector<4xi1>, %arg1: vector<4xi1>) {
   // CHECK: %{{.*}} = llvm.icmp "ne" %{{.*}}, %{{.*}} : !llvm<"<4 x i1>">
   %0 = spv.LogicalNotEqual %arg0, %arg0 : vector<4xi1>
   return
 }
 
 //===----------------------------------------------------------------------===//
+// spv.LogicalNot
+//===----------------------------------------------------------------------===//
+
+func @logical_not__scalar(%arg0: i1) {
+  // CHECK: %[[CONST:.*]] = llvm.mlir.constant(true) : !llvm.i1
+  // CHECK: %{{.*}} = llvm.xor %{{.*}}, %[[CONST]] : !llvm.i1
+  %0 = spv.LogicalNot %arg0 : i1
+  return
+}
+
+func @logical_not_vector(%arg0: vector<4xi1>) {
+  // CHECK: %[[CONST:.*]] = llvm.mlir.constant(dense<true> : vector<4xi1>) : !llvm<"<4 x i1>">
+  // CHECK: %{{.*}} = llvm.xor %{{.*}}, %[[CONST]] : !llvm<"<4 x i1>">
+  %0 = spv.LogicalNot %arg0 : vector<4xi1>
+  return
+}
+
+//===----------------------------------------------------------------------===//
 // spv.LogicalAnd
 //===----------------------------------------------------------------------===//
 
 func @logical_and_scalar(%arg0: i1, %arg1: i1) {
   // CHECK: %{{.*}} = llvm.and %{{.*}}, %{{.*}} : !llvm.i1
   %0 = spv.LogicalAnd %arg0, %arg0 : i1
   return
 }