[RegisterCoalescer] Dumper for JoinVals

[vpykhtin]

Summary

Example:

RHSVals %1:sub0:
              0@128r Write:0000000000000003 Valid:0000000000000003 Keep -> 0@128r
               1@80r Write:0000000000000003 Valid:0000000000000003 Erase Other:1@64r -> 1@64r
          2@160B-phi Write:0000000000000003 Valid:0000000000000003 Merge Other:3@160B-phi -> 3@160B-phi

Helps a lot to understand what's going on.

The output can also be seen at: https://reviews.llvm.org/D82258

[arsenm]

llvm/lib/CodeGen/LiveInterval.cpp

1028

It should print each on a different line?

llvm/lib/CodeGen/RegisterCoalescer.cpp

3338–3339

Merge to one LLVM_DEBUG block

3436–3437

Merge to one LLVM_DEBUG block

[vpykhtin]

llvm/lib/CodeGen/LiveInterval.cpp

1028

No, why?

[arsenm]

llvm/lib/CodeGen/LiveInterval.cpp

1028

You manually corrected the output to make it readable, since the one line is way too long. Why not just print it that way?

[vpykhtin]

llvm/lib/CodeGen/LiveInterval.cpp

1028

I was trying to keep the style of dump it currently have, having less lines on output. I agree it much easier to read it formatted on different lines, so I'll probable change it.

[arsenm]

llvm/lib/CodeGen/LiveInterval.cpp

1028

I think the overly long line style is an obstacle to debugging. Whenever debugging livenes problems I end up manually breaking all of these up too

[vpykhtin]

Rebased, per review issues fixed, moved VNInfo::print definition ot of class.

[vpykhtin]

Ping

[arsenm]

llvm/lib/CodeGen/RegisterCoalescer.cpp

2343

Comma operator here is definitely weird. Braces and separate lines?

2344–2347

Separate lines

llvm/include/llvm/CodeGen/LiveInterval.h

public:
     /// EC slots.
     bool isPHIDef() const { return def.isBlock(); }
 
     /// Returns true if this value is unused.
     bool isUnused() const { return !def.isValid(); }
 
     /// Mark this value as unused.
     void markUnused() { def = SlotIndex(); }
+
+    void print(raw_ostream &OS) const;
   };
 
   /// Result of a LiveRange query. This class hides the implementation details
   /// of live ranges, and it should be used as the primary interface for
   /// examining live ranges around instructions.
   class LiveQueryResult {
     VNInfo *const EarlyVal;
     VNInfo *const LateVal;

llvm/lib/CodeGen/LiveInterval.cpp

void LiveRange::print(raw_ostream &OS) const {
   // Print value number info.
   if (getNumValNums()) {
     OS << "  ";
     unsigned vnum = 0;
     for (const_vni_iterator i = vni_begin(), e = vni_end(); i != e;
          ++i, ++vnum) {
       const VNInfo *vni = *i;
       if (vnum) OS << ' ';
-      OS << vnum << '@';
-      if (vni->isUnused()) {
-        OS << 'x';
-      } else {
-        OS << vni->def;
-        if (vni->isPHIDef())
-          OS << "-phi";
-      }
-    }
-  }
-}
+      vni->print(OS);
+    }
+  }
+}
+
+void VNInfo::print(raw_ostream &OS) const {
+  OS << id << '@';
+  if (isUnused()) {
+    OS << def;
+    if (isPHIDef())
 
 void LiveInterval::SubRange::print(raw_ostream &OS) const {
   OS << " L" << PrintLaneMask(LaneMask) << ' '
      << static_cast<const LiveRange&>(*this);
 }
 
 void LiveInterval::print(raw_ostream &OS) const {
   OS << printReg(reg) << ' ';

llvm/lib/CodeGen/RegisterCoalescer.cpp

 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the generic RegisterCoalescer interface which
struct Val {
     /// copy is redundant, i.e. the source value is already the same as
     /// the destination. In such cases the subranges need to be updated
     /// properly. See comment at pruneSubRegValues for more info.
     bool Identical = false;
 
     Val() = default;
 
     bool isAnalyzed() const { return WriteLanes.any(); }
+
+    void print(raw_ostream &O) const {
+      O << " Write:" << PrintLaneMask(WriteLanes)
+        << " Valid:" << PrintLaneMask(ValidLanes) << ' ';
+      switch(Resolution) {
+      case CR_Unresolved: O << "Unresolved"; return;
+      case CR_Impossible: O << "Impossible"; return;
+      case CR_Keep: O << "Keep"; break;
+      case CR_Replace: O << "Replace"; break;
+      case CR_Merge: O << "Merge"; break;
+      case CR_Erase: O << "Erase";
+        if (Identical) O << " Identical";
+      break;
+      }
+      if (OtherVNI) O << " Other:", OtherVNI->print(O);
+      if (RedefVNI) O << " Redef:", RedefVNI->print(O);
+      if (ErasableImplicitDef) O << " ImpDef";
+      if (Pruned || PrunedComputed) O << ' ' << (Pruned ? "Pruned" : "NonPruned");
+      if (PrunedComputed) O << 'C';
+    }
   };
 
   /// One entry per value number in LI.
   SmallVector<Val, 8> Vals;
 
   /// Compute the bitmask of lanes actually written by DefMI.
   /// Set Redef if there are any partial register definitions that depend on the
   /// previous value of the register.
public:
 
   /// Get the value assignments suitable for passing to LiveInterval::join.
   const int *getAssignments() const { return Assignments.data(); }
 
   /// Get the conflict resolution for a value number.
   ConflictResolution getResolution(unsigned Num) const {
     return Vals[Num].Resolution;
   }
+
+  void print(raw_ostream &O) const {
+    O << printReg(Register(Reg), TRI, SubIdx);
+    if (SubRangeJoin) O << ':' << PrintLaneMask(LaneMask);
+    O << ":\n";
+    std::string FormBuff;
+    for (unsigned ValNo = 0, E = Vals.size(); ValNo < E; ++ValNo) {
+      auto *VNI = LR.getValNumInfo(ValNo);
+      raw_string_ostream SS(FormBuff);
+      VNI->print(SS);
+      O << "\t\t" << right_justify(SS.str(), 20);
+      FormBuff.clear();
+      Vals[ValNo].print(O);
+      if (Assignments[ValNo] != -1) {
+        O << " -> ";
+        NewVNInfo[Assignments[ValNo]]->print(O);
+      }
+      O << '\n';
+    }
+  }
+
+  LLVM_DUMP_METHOD void dump() const {
+    print(dbgs());
+  }
 };
 
 } // end anonymous namespace
 
 LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
   const {
   LaneBitmask L;
   for (const MachineOperand &MO : DefMI->operands()) {
void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
   }
   if (!LHSVals.resolveConflicts(RHSVals) ||
       !RHSVals.resolveConflicts(LHSVals)) {
     // We already determined that it is legal to merge the intervals, so this
     // should never fail.
     llvm_unreachable("*** Couldn't join subrange!\n");
   }
 
+  LLVM_DEBUG(
+    dbgs() << "\t\tRHSVals "; RHSVals.dump();
+    dbgs() << "\n\t\tLHSVals "; LHSVals.dump();
+    dbgs() << '\n'
+  );
+
   // The merging algorithm in LiveInterval::join() can't handle conflicting
   // value mappings, so we need to remove any live ranges that overlap a
   // CR_Replace resolution. Collect a set of end points that can be used to
   // restore the live range after joining.
   SmallVector<SlotIndex, 8> EndPoints;
   LHSVals.pruneValues(RHSVals, EndPoints, false);
   RHSVals.pruneValues(LHSVals, EndPoints, false);
 
bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
   // Detect impossible conflicts early.
   if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
     return false;
 
   // Some conflicts can only be resolved after all values have been mapped.
   if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
     return false;
 
+  LLVM_DEBUG(
+    dbgs() << "\t\tRHSVals "; RHSVals.dump();
+    dbgs() << "\n\t\tLHSVals "; LHSVals.dump();
+    dbgs() << '\n'
+  );
+
   // All clear, the live ranges can be merged.
   if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
     BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
 
     // Transform lanemasks from the LHS to masks in the coalesced register and
     // create initial subranges if necessary.
     unsigned DstIdx = CP.getDstIdx();
     if (!LHS.hasSubRanges()) {