[MSAN] Handle x86 {round,min,max}sd intrinsics

[guiand]

Summary

These need special handling over the simple vector intrinsics as they behave more like a shuffle operation: taking the top half of the vector from one input, and the bottom half separately. Previously, these were being handled as though all bits of all operands were combined.

[guiand]

Ran clang-format

[eugenis]

The test should be in LLVM, under test/Instrumentation/MemorySanitizer

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

3069

You probably want to insert in First, not Second.

Is the generated code any better if you OR the vectors, and then shuffle to put the top element of First into the top element of the output? That's what LLVM generates if I express this logic in C.

[guiand]

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

3069

The codegen is basically identical either way, but if you'd like I can still upload a patch to change these into shufflevector instructions.

[guiand]

Use shufflevector, move test over to IR

[eugenis]

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

3069

This is much better.
Use makeArrayRef({2, 1}).

3323

Unrelated change.

llvm/test/Instrumentation/MemorySanitizer/vector_sd.ll

17 ↗

(On Diff #272842)

pass the vectors as arguments, it will make the test case a lot simpler

[guiand]

Addressed comments

[guiand]

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

3323

Whoops!

[eugenis]

LGTM

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

3069

llvm:: is unnecessary, and <int> is probably too

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Value *Shuf1 =
         IRB.CreateShuffleVector(getShadow(&I, 1), UndefValue::get(ShadowTy),
                                 getPclmulMask(Width, Imm & 0x10));
     ShadowAndOriginCombiner SOC(this, IRB);
     SOC.Add(Shuf0, getOrigin(&I, 0));
     SOC.Add(Shuf1, getOrigin(&I, 1));
     SOC.Done(&I);
   }
 
+  // Instrument _mm_*_sd intrinsics
+  void handleUnarySdIntrinsic(IntrinsicInst &I) {
+    IRBuilder<> IRB(&I);
+    Value *First = getShadow(&I, 0);
+    Value *Second = getShadow(&I, 1);
+    // High word of first operand, low word of second
+    Value *Shadow =
+        IRB.CreateShuffleVector(First, Second, llvm::makeArrayRef<int>({2, 1}));
+
+    setShadow(&I, Shadow);
+    setOriginForNaryOp(I);
+  }
+
+  void handleBinarySdIntrinsic(IntrinsicInst &I) {
+    IRBuilder<> IRB(&I);
+    Value *First = getShadow(&I, 0);
+    Value *Second = getShadow(&I, 1);
+    Value *OrShadow = IRB.CreateOr(First, Second);
+    // High word of first operand, low word of both OR'd together
+    Value *Shadow = IRB.CreateShuffleVector(First, OrShadow,
+                                            llvm::makeArrayRef<int>({2, 1}));
+
+    setShadow(&I, Shadow);
+    setOriginForNaryOp(I);
+  }
+
   void visitIntrinsicInst(IntrinsicInst &I) {
     switch (I.getIntrinsicID()) {
     case Intrinsic::lifetime_start:
       handleLifetimeStart(I);
       break;
     case Intrinsic::launder_invariant_group:
     case Intrinsic::strip_invariant_group:
       handleInvariantGroup(I);
case Intrinsic::x86_bmi_pext_64:
       break;
 
     case Intrinsic::x86_pclmulqdq:
     case Intrinsic::x86_pclmulqdq_256:
     case Intrinsic::x86_pclmulqdq_512:
       handlePclmulIntrinsic(I);
       break;
 
+    case Intrinsic::x86_sse41_round_sd:
+      handleUnarySdIntrinsic(I);
+      break;
+    case Intrinsic::x86_sse2_max_sd:
+    case Intrinsic::x86_sse2_min_sd:
+      handleBinarySdIntrinsic(I);
+      break;
+
     case Intrinsic::is_constant:
       // The result of llvm.is.constant() is always defined.
       setShadow(&I, getCleanShadow(&I));
       setOrigin(&I, getCleanOrigin());
       break;
 
     default:
       if (!handleUnknownIntrinsic(I))
         visitInstruction(I);
       break;