[MSP430] Update register names

[atrosinenko]

Summary

When writing a unit test on replacing standard epilogue sequences with BR __mspabi_func_epilog_<N>, by manually asm-clobbering rN - r10 for N = 4..10, everything worked well except for seeming inability to clobber r4.

The problem was that MSP430 code generator of LLVM used an obsolete name FP for that register. Things were worse because when llc read an unknown register name, it silently ignored it.

Example: take the following source:

test-regs.c

void f(void)
{
  asm volatile ("" : : : "r0");
  asm volatile ("" : : : "r1");
  asm volatile ("" : : : "r2");
  asm volatile ("" : : : "r3");
  asm volatile ("" : : : "r4");
  asm volatile ("" : : : "r5");
}

void g(void)
{
  asm volatile ("" : : : "pc");
  asm volatile ("" : : : "sp");
  asm volatile ("" : : : "sr");
  asm volatile ("" : : : "cg");
  asm volatile ("" : : : "fp");
  asm volatile ("" : : : "r5");
}

and execute:

$ $sysroot/bin/msp430-elf-gcc --version
msp430-elf-gcc (Mitto Systems Limited - msp430-gcc 8.3.1.25) 8.3.1
Copyright (C) 2018 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

$ $sysroot/bin/msp430-elf-gcc -c test-regs.c
test-regs.c: In function 'g':
test-regs.c:14:3: error: unknown register name 'pc' in 'asm'
   asm volatile ("" : : : "pc");
   ^~~
test-regs.c:15:3: error: unknown register name 'sp' in 'asm'
   asm volatile ("" : : : "sp");
   ^~~
test-regs.c:16:3: error: unknown register name 'sr' in 'asm'
   asm volatile ("" : : : "sr");
   ^~~
test-regs.c:17:3: error: unknown register name 'cg' in 'asm'
   asm volatile ("" : : : "cg");
   ^~~
test-regs.c:18:3: error: unknown register name 'fp' in 'asm'
   asm volatile ("" : : : "fp");
   ^~~
$ clang --version
clang version 10.0.0-4ubuntu1 
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/bin
$ clang -target msp430 -c test-regs.c 
test-regs.c:14:26: error: unknown register name 'pc' in asm
  asm volatile ("" : : : "pc");
                         ^
test-regs.c:15:26: error: unknown register name 'sp' in asm
  asm volatile ("" : : : "sp");
                         ^
test-regs.c:16:26: error: unknown register name 'sr' in asm
  asm volatile ("" : : : "sr");
                         ^
test-regs.c:17:26: error: unknown register name 'cg' in asm
  asm volatile ("" : : : "cg");
                         ^
test-regs.c:18:26: error: unknown register name 'fp' in asm
  asm volatile ("" : : : "fp");
                         ^
5 errors generated.

No differences at all. Now, let's drop g() function, to make it valid source.

$ clang -target msp430 test-regs.c -S -emit-llvm -o-
...
; Function Attrs: noinline nounwind optnone
define dso_local void @f() #0 {
  call void asm sideeffect "", "~{r0}"() #1, !srcloc !2
  call void asm sideeffect "", "~{r1}"() #1, !srcloc !3
  call void asm sideeffect "", "~{r2}"() #1, !srcloc !4
  call void asm sideeffect "", "~{r3}"() #1, !srcloc !5
  call void asm sideeffect "", "~{r4}"() #1, !srcloc !6
  call void asm sideeffect "", "~{r5}"() #1, !srcloc !7
  ret void
}
...

Everything looks good, again.

$ clang -target msp430 test-regs.c -S -mllvm -stop-after=finalize-isel -o-
...
body:             |
  bb.0 (%ir-block.0):
    INLINEASM &"", 1, !2
    INLINEASM &"", 1, !3
    INLINEASM &"", 1, !4
    INLINEASM &"", 1, !5
    INLINEASM &"", 1, !6
    INLINEASM &"", 1, 12, implicit-def early-clobber $r5, !7
    RET

That is, I cannot use fp register name from the C code because Clang does not accept it (exactly like GCC). But the accepted name r4 is not recognised by llc (it can be used in listings passed to llvm-mc and even fp is replace to r4 by llvm-mc). So I can specify any of fp or r4 for the string literal of asm(...) but nothing in the clobber list.

This patch replaces MSP430::FP with MSP430::R4 in the backend code (even MSP430 EABI doesn't mention FP as a register name). The R0 - R3 registers, on the other hand, are left as is in the backend code (after all, they have some special meaning on the ISA level). It is just ensured clang is renaming them as expected by the downstream tools. There is probably not much sense in marking them clobbered but rename them just in case for use at potentially different contexts.

[asl]

Looks good to me! FP was an old register name from mspgcc time. MSP430 EABI does not use frame pointer at all (seems to be a bug in the ABI, as I do not understand how we could support VLAs or alloca's in this case).

[atrosinenko]

Fix compile error when building with older compilers.

clang/lib/Basic/Targets/MSP430.h

public:
 
   bool hasFeature(StringRef Feature) const override {
     return Feature == "msp430";
   }
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
-    // No aliases.
-    return None;
+    // Make r0 - r3 be recognized by llc (f.e., in clobber list)
+    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
+        {{"r0"}, "pc"},
+        {{"r1"}, "sp"},
+        {{"r2"}, "sr"},
+        {{"r3"}, "cg"},
+    };
+    return GCCRegAliases;
   }
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &info) const override {
     // FIXME: implement
     switch (*Name) {
     case 'K': // the constant 1
     case 'L': // constant -1^20 .. 1^19

clang/test/CodeGen/msp430-register-names.c

+// Registers R0 - R3 have different names inside the LLVM MSP430 target code.
+// Test that they are handled properly when used inside clobber lists.
+// At the time of writing, llc silently ignores unknown register names.
+
+// REQUIRES: msp430-registered-target
+// RUN: %clang -target msp430 -c %s -mllvm -stop-after=finalize-isel -o- | FileCheck %s
+
+void test_function(void) {
+  asm volatile(""
+               :
+               :
+               : "r0");
+  asm volatile(""
+               :
+               :
+               : "r1");
+  asm volatile(""
+               :
+               :
+               : "r2");
+  asm volatile(""
+               :
+               :
+               : "r3");
+  asm volatile(""
+               :
+               :
+               : "r4");
+  asm volatile(""
+               :
+               :
+               : "r5");
+  asm volatile(""
+               :
+               :
+               : "r6");
+  asm volatile(""
+               :
+               :
+               : "r7");
+  asm volatile(""
+               :
+               :
+               : "r8");
+  asm volatile(""
+               :
+               :
+               : "r9");
+  asm volatile(""
+               :
+               :
+               : "r10");
+  asm volatile(""
+               :
+               :
+               : "r11");
+  asm volatile(""
+               :
+               :
+               : "r12");
+  asm volatile(""
+               :
+               :
+               : "r13");
+  asm volatile(""
+               :
+               :
+               : "r14");
+  asm volatile(""
+               :
+               :
+               : "r15");
+  // CHECK: call void asm sideeffect "", "~{pc}"()
+  // CHECK: call void asm sideeffect "", "~{sp}"()
+  // CHECK: call void asm sideeffect "", "~{sr}"()
+  // CHECK: call void asm sideeffect "", "~{cg}"()
+  // CHECK: call void asm sideeffect "", "~{r4}"()
+  // CHECK: call void asm sideeffect "", "~{r5}"()
+  // CHECK: call void asm sideeffect "", "~{r6}"()
+  // CHECK: call void asm sideeffect "", "~{r7}"()
+  // CHECK: call void asm sideeffect "", "~{r8}"()
+  // CHECK: call void asm sideeffect "", "~{r9}"()
+  // CHECK: call void asm sideeffect "", "~{r10}"()
+  // CHECK: call void asm sideeffect "", "~{r11}"()
+  // CHECK: call void asm sideeffect "", "~{r12}"()
+  // CHECK: call void asm sideeffect "", "~{r13}"()
+  // CHECK: call void asm sideeffect "", "~{r14}"()
+  // CHECK: call void asm sideeffect "", "~{r15}"()
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $pc
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $sp
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $sr
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $cg
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r4
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r5
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r6
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r7
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r8
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r9
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r10
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r11
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r12
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r13
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r14
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $r15
+}

llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp

 static unsigned convertGR16ToGR8(unsigned Reg) {
   switch (Reg) {
   default:
     llvm_unreachable("Unknown GR16 register");
   case MSP430::PC:  return MSP430::PCB;
   case MSP430::SP:  return MSP430::SPB;
   case MSP430::SR:  return MSP430::SRB;
   case MSP430::CG:  return MSP430::CGB;
-  case MSP430::FP:  return MSP430::FPB;
+  case MSP430::R4:  return MSP430::R4B;
   case MSP430::R5:  return MSP430::R5B;
   case MSP430::R6:  return MSP430::R6B;
   case MSP430::R7:  return MSP430::R7B;
   case MSP430::R8:  return MSP430::R8B;
   case MSP430::R9:  return MSP430::R9B;
   case MSP430::R10: return MSP430::R10B;
   case MSP430::R11: return MSP430::R11B;
   case MSP430::R12: return MSP430::R12B;

llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp

 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430Disassembler() {
   TargetRegistry::RegisterMCDisassembler(getTheMSP430Target(),
                                          createMSP430Disassembler);
 }
 
 static const unsigned GR8DecoderTable[] = {
   MSP430::PCB,  MSP430::SPB,  MSP430::SRB,  MSP430::CGB,
-  MSP430::FPB,  MSP430::R5B,  MSP430::R6B,  MSP430::R7B,
+  MSP430::R4B,  MSP430::R5B,  MSP430::R6B,  MSP430::R7B,
   MSP430::R8B,  MSP430::R9B,  MSP430::R10B, MSP430::R11B,
   MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B
 };
 
 static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo,
                                            uint64_t Address,
                                            const void *Decoder) {
   if (RegNo > 15)
     return MCDisassembler::Fail;
 
   unsigned Reg = GR8DecoderTable[RegNo];
   MI.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static const unsigned GR16DecoderTable[] = {
   MSP430::PC,  MSP430::SP,  MSP430::SR,  MSP430::CG,
-  MSP430::FP,  MSP430::R5,  MSP430::R6,  MSP430::R7,
+  MSP430::R4,  MSP430::R5,  MSP430::R6,  MSP430::R7,
   MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
   MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
 };
 
 static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   if (RegNo > 15)

llvm/lib/Target/MSP430/MSP430FrameLowering.cpp

if (hasFP(MF)) {
 
     // Get the offset of the stack slot for the EBP register... which is
     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
     // Update the frame offset adjustment.
     MFI.setOffsetAdjustment(-NumBytes);
 
     // Save FP into the appropriate stack slot...
     BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
-      .addReg(MSP430::FP, RegState::Kill);
+      .addReg(MSP430::R4, RegState::Kill);
 
     // Update FP with the new base value...
-    BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
+    BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4)
       .addReg(MSP430::SP);
 
     // Mark the FramePtr as live-in in every block except the entry.
     for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
          I != E; ++I)
-      I->addLiveIn(MSP430::FP);
+      I->addLiveIn(MSP430::R4);
 
   } else
     NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
 
   // Skip the callee-saved push instructions.
   while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
     ++MBBI;
 
void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
   uint64_t NumBytes = 0;
 
   if (hasFP(MF)) {
     // Calculate required stack adjustment
     uint64_t FrameSize = StackSize - 2;
     NumBytes = FrameSize - CSSize;
 
     // pop FP.
-    BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
+    BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4);
   } else
     NumBytes = StackSize - CSSize;
 
   // Skip the callee-saved pop instructions.
   while (MBBI != MBB.begin()) {
     MachineBasicBlock::iterator PI = std::prev(MBBI);
     unsigned Opc = PI->getOpcode();
     if (Opc != MSP430::POP16r && !PI->isTerminator())
       break;
     --MBBI;
   }
 
   DL = MBBI->getDebugLoc();
 
   // If there is an ADD16ri or SUB16ri of SP immediately before this
   // instruction, merge the two instructions.
   //if (NumBytes || MFI.hasVarSizedObjects())
   //  mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
 
   if (MFI.hasVarSizedObjects()) {
     BuildMI(MBB, MBBI, DL,
-            TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
+            TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4);
     if (CSSize) {
       MachineInstr *MI =
         BuildMI(MBB, MBBI, DL,
                 TII.get(MSP430::SUB16ri), MSP430::SP)
         .addReg(MSP430::SP).addImm(CSSize);
       // The SRW implicit def is dead.
       MI->getOperand(3).setIsDead();
     }

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
                                              SelectionDAG &DAG) const {
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
   MFI.setFrameAddressIsTaken(true);
 
   EVT VT = Op.getValueType();
   SDLoc dl(Op);  // FIXME probably not meaningful
   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
-                                         MSP430::FP, VT);
+                                         MSP430::R4, VT);
   while (Depth--)
     FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
                             MachinePointerInfo());
   return FrameAddr;
 }
 
 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
                                            SelectionDAG &DAG) const {

llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp

 MSP430RegisterInfo::MSP430RegisterInfo()
   : MSP430GenRegisterInfo(MSP430::PC) {}
 
 const MCPhysReg*
 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   const MSP430FrameLowering *TFI = getFrameLowering(*MF);
   const Function* F = &MF->getFunction();
   static const MCPhysReg CalleeSavedRegs[] = {
-    MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
+    MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
     MSP430::R8, MSP430::R9, MSP430::R10,
     0
   };
   static const MCPhysReg CalleeSavedRegsFP[] = {
     MSP430::R5, MSP430::R6, MSP430::R7,
     MSP430::R8, MSP430::R9, MSP430::R10,
     0
   };
   static const MCPhysReg CalleeSavedRegsIntr[] = {
-    MSP430::FP,  MSP430::R5,  MSP430::R6,  MSP430::R7,
+    MSP430::R4,  MSP430::R5,  MSP430::R6,  MSP430::R7,
     MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
     0
   };
   static const MCPhysReg CalleeSavedRegsIntrFP[] = {
     MSP430::R5,  MSP430::R6,  MSP430::R7,
     MSP430::R8,  MSP430::R9,  MSP430::R10, MSP430::R11,
     MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   Reserved.set(MSP430::CGB);
   Reserved.set(MSP430::PC);
   Reserved.set(MSP430::SP);
   Reserved.set(MSP430::SR);
   Reserved.set(MSP430::CG);
 
   // Mark frame pointer as reserved if needed.
   if (TFI->hasFP(MF)) {
-    Reserved.set(MSP430::FPB);
-    Reserved.set(MSP430::FP);
+    Reserved.set(MSP430::R4B);
+    Reserved.set(MSP430::R4);
   }
 
   return Reserved;
 }
 
 const TargetRegisterClass *
 MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
                                                                          const {
   return &MSP430::GR16RegClass;
 }
 
 void
 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                         int SPAdj, unsigned FIOperandNum,
                                         RegScavenger *RS) const {
   assert(SPAdj == 0 && "Unexpected");
 
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
   const MSP430FrameLowering *TFI = getFrameLowering(MF);
   DebugLoc dl = MI.getDebugLoc();
   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
 
-  unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP);
+  unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP);
   int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
 
   // Skip the saved PC
   Offset += 2;
 
   if (!TFI->hasFP(MF))
     Offset += MF.getFrameInfo().getStackSize();
   else
MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
 }
 
 Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const MSP430FrameLowering *TFI = getFrameLowering(MF);
-  return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
+  return TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP;
 }

llvm/lib/Target/MSP430/MSP430RegisterInfo.td

 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
 def PCB  : MSP430Reg<0,  "r0", ["pc"]>;
 def SPB  : MSP430Reg<1,  "r1", ["sp"]>;
 def SRB  : MSP430Reg<2,  "r2", ["sr"]>;
 def CGB  : MSP430Reg<3,  "r3", ["cg"]>;
-def FPB  : MSP430Reg<4,  "r4", ["fp"]>;
+def R4B  : MSP430Reg<4,  "r4", ["fp"]>;
 def R5B  : MSP430Reg<5,  "r5">;
 def R6B  : MSP430Reg<6,  "r6">;
 def R7B  : MSP430Reg<7,  "r7">;
 def R8B  : MSP430Reg<8,  "r8">;
 def R9B  : MSP430Reg<9,  "r9">;
 def R10B : MSP430Reg<10, "r10">;
 def R11B : MSP430Reg<11, "r11">;
 def R12B : MSP430Reg<12, "r12">;
 def R13B : MSP430Reg<13, "r13">;
 def R14B : MSP430Reg<14, "r14">;
 def R15B : MSP430Reg<15, "r15">;
 
 def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
 
 let SubRegIndices = [subreg_8bit] in {
 def PC  : MSP430RegWithSubregs<0,  "r0",  [PCB], ["pc"]>;
 def SP  : MSP430RegWithSubregs<1,  "r1",  [SPB], ["sp"]>;
 def SR  : MSP430RegWithSubregs<2,  "r2",  [SRB], ["sr"]>;
 def CG  : MSP430RegWithSubregs<3,  "r3",  [CGB], ["cg"]>;
-def FP  : MSP430RegWithSubregs<4,  "r4",  [FPB], ["fp"]>;
+def R4  : MSP430RegWithSubregs<4,  "r4",  [R4B], ["fp"]>;
 def R5  : MSP430RegWithSubregs<5,  "r5",  [R5B]>;
 def R6  : MSP430RegWithSubregs<6,  "r6",  [R6B]>;
 def R7  : MSP430RegWithSubregs<7,  "r7",  [R7B]>;
 def R8  : MSP430RegWithSubregs<8,  "r8",  [R8B]>;
 def R9  : MSP430RegWithSubregs<9,  "r9",  [R9B]>;
 def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>;
 def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
 def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
 def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
 def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
 }
 
 def GR8 : RegisterClass<"MSP430", [i8], 8,
    // Volatile registers
   (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
    // Frame pointer, sometimes allocable
-   FPB,
+   R4B,
    // Volatile, but not allocable
    PCB, SPB, SRB, CGB)>;
 
 def GR16 : RegisterClass<"MSP430", [i16], 16,
    // Volatile registers
   (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
    // Frame pointer, sometimes allocable
-   FP,
+   R4,
    // Volatile, but not allocable
    PC, SP, SR, CG)>;

llvm/test/CodeGen/MSP430/asm-clobbers.ll

 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"
 target triple = "msp430---elf"
 
-define void @test() {
+define void @test_no_clobber() {
 entry:
-; CHECK-LABEL: test:
+; CHECK-LABEL: test_no_clobber
+; CHECK-NOT: push
+  call void asm sideeffect "", ""()
+; CHECK-NOT: pop
+  ret void
+; CHECK: -- End function
+}
+
+define void @test_1() {
+entry:
+; CHECK-LABEL: test_1:
+; CHECK: push r8
+; CHECK: push r6
+; CHECK: push r4
+  call void asm sideeffect "", "~{r4},~{r6},~{r8}"()
+; CHECK: pop r4
+; CHECK: pop r6
+; CHECK: pop r8
+  ret void
+}
+
+define void @test_2() {
+entry:
+; CHECK-LABEL: test_2:
+; CHECK: push r9
+; CHECK: push r7
+; CHECK: push r5
+  call void asm sideeffect "", "~{r5},~{r7},~{r9}"()
+; CHECK: pop r5
+; CHECK: pop r7
+; CHECK: pop r9
+  ret void
+}
+
+; The r10 register is special because the sequence
+;   pop r10
+;   ret
+; can be replaced with
+;   jmp __mspabi_func_epilog_1
+; or other such function (depending on previous instructions).
+; Still, it is not replaced *yet*.
+define void @test_r10() {
+entry:
+; CHECK-LABEL: test_r10:
 ; CHECK: push r10
   call void asm sideeffect "", "~{r10}"()
 ; CHECK: pop r10
   ret void
 }

llvm/test/CodeGen/MSP430/inline-asm-register-names.ll

+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+; Test that correct register names are accepted *inside* inline asm listings.
+; Tested with PUSH instruction since it does not support memory operands.
+
+define void @accepted_rN() nounwind {
+; CHECK-LABEL: accepted_rN
+  call void asm sideeffect "push r0", ""() nounwind
+; CHECK: push r0
+  call void asm sideeffect "push r1", ""() nounwind
+; CHECK: push r1
+  call void asm sideeffect "push r2", ""() nounwind
+; CHECK: push r2
+  call void asm sideeffect "push r3", ""() nounwind
+; CHECK: push r3
+  call void asm sideeffect "push r4", ""() nounwind
+; CHECK: push r4
+  call void asm sideeffect "push r5", ""() nounwind
+; CHECK: push r5
+  call void asm sideeffect "push r6", ""() nounwind
+; CHECK: push r6
+  call void asm sideeffect "push r7", ""() nounwind
+; CHECK: push r7
+  call void asm sideeffect "push r8", ""() nounwind
+; CHECK: push r8
+  call void asm sideeffect "push r9", ""() nounwind
+; CHECK: push r9
+  call void asm sideeffect "push r10", ""() nounwind
+; CHECK: push r10
+  call void asm sideeffect "push r11", ""() nounwind
+; CHECK: push r11
+  call void asm sideeffect "push r12", ""() nounwind
+; CHECK: push r12
+  call void asm sideeffect "push r13", ""() nounwind
+; CHECK: push r13
+  call void asm sideeffect "push r14", ""() nounwind
+; CHECK: push r14
+  call void asm sideeffect "push r15", ""() nounwind
+; CHECK: push r15
+  ret void
+}
+
+define void @accepted_reg_aliases() nounwind {
+; CHECK-LABEL: accepted_reg_aliases
+; Ensure register aliases are renamed as expected
+call void asm sideeffect "push pc", ""() nounwind
+; CHECK: push r0
+call void asm sideeffect "push sp", ""() nounwind
+; CHECK: push r1
+call void asm sideeffect "push sr", ""() nounwind
+; CHECK: push r2
+call void asm sideeffect "push cg", ""() nounwind
+; CHECK: push r3
+call void asm sideeffect "push fp", ""() nounwind
+; CHECK: push r4
+        ret void
+}