GlobalISel: Verify G_BITCAST changes the type

[arsenm]

Summary

Updated the AArch64 tests the best I could with my vague, inferred
understanding of AArch64 register banks. As far as I can tell, there
is only one 32-bit/64-bit type which will use the gpr register bank,
so we have to use the fpr bank for the other operand.

[arsenm]

ping

[paquette]

There are a couple places in the AArch64 tests where there are vectors on GPR registers. AFAIK we always want vectors on FPRs.

@aemerson should this happen?

llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

410

AFAIK we should only have vectors on FPRs, but maybe I'm wrong about that.

@aemerson ?

[arsenm]

ping

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

410

We never enable the greedy RBS mode. I think this behavior is wrong for vectors.

[arsenm]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

410

For the purpose of the patch, there just needs to be something here to test a bitcast. If it happens to produce the wrong output, that's a separate issue

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

410

Please add a comment in this test to explain that the greedy checks are correct.

[arsenm]

74a148ad39ab32317948a2d6291264acd84bfa00

llvm/lib/CodeGen/MachineVerifier.cpp

case TargetOpcode::G_BITCAST: {
     if (!DstTy.isValid() || !SrcTy.isValid())
       break;
 
     if (SrcTy.isPointer() != DstTy.isPointer())
       report("bitcast cannot convert between pointers and other types", MI);
 
     if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
       report("bitcast sizes must match", MI);
+
+    if (SrcTy == DstTy)
+      report("bitcast must change the type", MI);
+
     break;
   }
   case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_ADDRSPACE_CAST: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
     if (!DstTy.isValid() || !SrcTy.isValid())

llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

 
 ---
 # CHECK-LABEL: name: bitcast_s32_gpr
 name:            bitcast_s32_gpr
 legalized:       true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0:gpr(s32) = COPY $w0
-# CHECK:    %1:gpr(s32) = G_BITCAST %0
+# FAST-NEXT:   %1:fpr(<4 x s8>) = G_BITCAST %0
+# GREEDY-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $w0
 
     %0(s32) = COPY $w0
-    %1(s32) = G_BITCAST %0
+    %1(<4 x s8>) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_fpr
 name:            bitcast_s32_fpr
 legalized:       true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0:fpr(<2 x s16>) = COPY $s0
-# CHECK:    %1:fpr(<2 x s16>) = G_BITCAST %0
+# FAST:     %1:gpr(s32) = G_BITCAST %0
+# GREEDY:   %1:fpr(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $s0
 
     %0(<2 x s16>) = COPY $s0
-    %1(<2 x s16>) = G_BITCAST %0
+    %1(s32) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s32_gpr_fpr
 name:            bitcast_s32_gpr_fpr
 legalized:       true
 
 # CHECK:      registers:

 # CHECK-LABEL: name: bitcast_s64_gpr
 name:            bitcast_s64_gpr
 legalized:       true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 # CHECK:  body:
 # CHECK:    %0:gpr(s64) = COPY $x0
-# CHECK:    %1:gpr(s64) = G_BITCAST %0
+# FAST:    %1:fpr(<2 x s32>) = G_BITCAST %0
+# GREEDY:  %1:gpr(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $x0
 
     %0(s64) = COPY $x0
-    %1(s64) = G_BITCAST %0
+    %1(<2 x s32>) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_fpr
 name:            bitcast_s64_fpr
 legalized:       true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 # CHECK:  body:
 # CHECK:    %0:fpr(<2 x s32>) = COPY $d0
-# CHECK:    %1:fpr(<2 x s32>) = G_BITCAST %0
+# FAST:     %1:gpr(s64) = G_BITCAST %0
+# GREEDY:   %1:fpr(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $d0
 
     %0(<2 x s32>) = COPY $d0
-    %1(<2 x s32>) = G_BITCAST %0
+    %1(s64) = G_BITCAST %0
 ...
 
 ---
 # CHECK-LABEL: name: bitcast_s64_gpr_fpr
 name:            bitcast_s64_gpr_fpr
 legalized:       true
 registers:
   - { id: 0, class: _ }

llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

body:             |
   ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
   ; CHECK:   $w0 = COPY [[COPY3]](s32)
   ; CHECK:   [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
   ; CHECK:   [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
   ; CHECK:   $x0 = COPY [[SELECT4]](s64)
   ; CHECK:   [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
   ; CHECK:   [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
   ; CHECK:   $x0 = COPY [[BITCAST1]](s64)
-  ; CHECK:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[SELECT3]](s32)
-  ; CHECK:   $w0 = COPY [[BITCAST2]](s32)
+  ; CHECK:   [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[SELECT3]](s32)
+  ; CHECK:   $w0 = COPY [[BITCAST2]](<2 x s16>)
   ; CHECK:   [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[TRUNC1]](s32)
   ; CHECK:   [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
   ; CHECK:   $w0 = COPY [[BITCAST4]](s32)
   ; CHECK:   [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[TRUNC1]](s32)
   ; CHECK:   [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
   ; CHECK:   $w0 = COPY [[BITCAST6]](s32)
   bb.0.entry:
     successors: %bb.1(0x80000000)
bb.1:
     %19:_(s32) = G_ANYEXT %9(s16)
     $w0 = COPY %19(s32)
     %10:_(s32) = G_SELECT %1(s1), %4, %4
     %11:_(s64) = G_SELECT %1(s1), %0, %0
     $x0 = COPY %11(s64)
     %12:_(<2 x s32>) = G_BITCAST %0(s64)
     %13:_(s64) = G_BITCAST %12(<2 x s32>)
     $x0 = COPY %13(s64)
-    %14:_(s32) = G_BITCAST %10(s32)
-    $w0 = COPY %14(s32)
+    %14:_(<2 x s16>) = G_BITCAST %10(s32)
+    $w0 = COPY %14
     %15:_(<4 x s8>) = G_BITCAST %4(s32)
     %20:_(s32) = G_BITCAST %15(<4 x s8>)
     $w0 = COPY %20(s32)
     %16:_(<2 x s16>) = G_BITCAST %4(s32)
     %21:_(s32) = G_BITCAST %16(<2 x s16>)
     $w0 = COPY %21(s32)
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir

 ...
 
 ---
 name:            bitcast_s32_gpr
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-
+  - { id: 1, class: fpr }
+  - { id: 2, class: gpr }
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: bitcast_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
-    ; CHECK: $w0 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: $w0 = COPY [[COPY2]]
     %0(s32) = COPY $w0
-    %1(s32) = G_BITCAST %0
-    $w0 = COPY %1(s32)
+    %1(<2 x s16>) = G_BITCAST %0
+    %2(s32) = G_BITCAST %1
+    $w0 = COPY %2
 ...
 
 ---
 name:            bitcast_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-
+  - { id: 1, class: gpr }
+  - { id: 2, class: fpr }
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: bitcast_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: $s0 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[COPY1]]
+    ; CHECK: $s0 = COPY [[COPY2]]
     %0(s32) = COPY $s0
-    %1(s32) = G_BITCAST %0
-    $s0 = COPY %1(s32)
+    %1(<2 x s16>) = G_BITCAST %0
+    %2(s32) = G_BITCAST %1
+    $s0 = COPY %2
 ...
 
 ---
 name:            bitcast_s32_gpr_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: bitcast_s32_gpr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
     ; CHECK: $s0 = COPY [[COPY1]]
     %0(s32) = COPY $w0
-    %1(s32) = G_BITCAST %0
-    $s0 = COPY %1(s32)
+    %1(<2 x s16>) = G_BITCAST %0
+    $s0 = COPY %1
 ...
 
 ---
 name:            bitcast_s32_fpr_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: bitcast_s32_fpr_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
     ; CHECK: $w0 = COPY [[COPY1]]
-    %0(s32) = COPY $s0
+    %0(<2 x s16>) = COPY $s0
     %1(s32) = G_BITCAST %0
     $w0 = COPY %1(s32)
 ...
 
 ---
 name:            bitcast_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: gpr }
 
 body:             |
   bb.0:
     liveins: $x0
 
     ; CHECK-LABEL: name: bitcast_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
-    ; CHECK: $x0 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
+    ; CHECK: $x0 = COPY [[COPY2]]
     %0(s64) = COPY $x0
-    %1(s64) = G_BITCAST %0
-    $x0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    %2(s64) = G_BITCAST %1
+    $x0 = COPY %2(s64)
 ...
 
 ---
 name:            bitcast_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: bitcast_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: $d0 = COPY [[COPY]]
     %0(s64) = COPY $d0
-    %1(s64) = G_BITCAST %0
-    $d0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    $d0 = COPY %1
 ...
 
 ---
 name:            bitcast_s64_gpr_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 body:             |
   bb.0:
     liveins: $x0
 
     ; CHECK-LABEL: name: bitcast_s64_gpr_fpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
     ; CHECK: $d0 = COPY [[COPY1]]
     %0(s64) = COPY $x0
-    %1(s64) = G_BITCAST %0
-    $d0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    $d0 = COPY %1
 ...
 
 ---
 name:            bitcast_s64_fpr_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: $d0
 
     ; CHECK-LABEL: name: bitcast_s64_fpr_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
     ; CHECK: $x0 = COPY [[COPY1]]
     %0(s64) = COPY $d0
-    %1(s64) = G_BITCAST %0
-    $x0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    $x0 = COPY %1
 ...
 
 ---
 name:            bitcast_s64_v2f32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
 name: bitcast_s
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0
     ; CHECK-LABEL: name: bitcast_s
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](s32)
+    ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
     %0:_(s32) = COPY $sgpr0
-    %1:_(s32) = G_BITCAST %0
+    %1:_(<2 x s16>) = G_BITCAST %0
 ...
 
 ---
 name: bitcast_v
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; CHECK-LABEL: name: bitcast_v
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[BITCAST:%[0-9]+]]:vgpr(s32) = G_BITCAST [[COPY]](s32)
+    ; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
     %0:_(s32) = COPY $vgpr0
-    %1:_(s32) = G_BITCAST %0
+    %1:_(<2 x s16>) = G_BITCAST %0
 ...

llvm/test/MachineVerifier/test_g_bitcast.mir

; CHECK:  Bad machine code: bitcast cannot convert between pointers and other types
     ; CHECK: Bad machine code: bitcast sizes must match
     %8:_(p1) = G_IMPLICIT_DEF
     %9:_(p3) = G_BITCAST %8
 
     ; CHECK: Bad machine code: bitcast sizes must match
     %10:_(p1) = G_IMPLICIT_DEF
     %11:_(p3) = G_BITCAST %8
 
+    ; CHECK: Bad machine code: bitcast must change the type
+    %12:_(s64) = G_BITCAST %0
 ...