[VE] Support fixed-point operation instructions in MC layer

[kaz7]

Summary

Add regression tests of asmparser, mccodeemitter, and disassembler for
fixed-point operation instructions. In order to support them, we add
MImm parser to asmparser. Also add a new MPD instruction which is one
of multiply instructions.

Depends on D81206.

[simoll]

Nits. Otw, LGTM. Thx!

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

366

[optional] You could use a const auto* here

707

typo

[kaz7]

Updated following suggestions.

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool ParseDirective(AsmToken DirectiveID) override;
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   // Custom parse functions for VE specific operands.
   OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
+  OperandMatchResultTy parseMImmOperand(OperandVector &Operands);
   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
   OperandMatchResultTy parseVEAsmOperand(std::unique_ptr<VEOperand> &Operand);
 
 public:
   VEAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
               const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
     // Initialize the set of available features.
enum KindTy {
     k_Token,
     k_Register,
     k_Immediate,
     // SX-Aurora ASX form is disp(index, base).
     k_MemoryRegRegImm,  // base=reg, index=reg, disp=imm
     k_MemoryRegImmImm,  // base=reg, index=imm, disp=imm
     k_MemoryZeroRegImm, // base=0, index=reg, disp=imm
     k_MemoryZeroImmImm, // base=0, index=imm, disp=imm
+    k_MImmOp,           // Special immediate value of sequential bit stream
+                        // of 0 or 1.
   } Kind;
 
   SMLoc StartLoc, EndLoc;
 
   struct Token {
     const char *Data;
     unsigned Length;
   };
 
   struct RegOp {
     unsigned RegNum;
   };
 
   struct ImmOp {
     const MCExpr *Val;
   };
 
   struct MemOp {
     unsigned Base;
     unsigned IndexReg;
     const MCExpr *Index;
     const MCExpr *Offset;
   };
 
+  struct MImmOp {
+    const MCExpr *Val;
+    bool M0Flag;
+  };
+
   union {
     struct Token Tok;
     struct RegOp Reg;
     struct ImmOp Imm;
     struct MemOp Mem;
+    struct MImmOp MImm;
   };
 
 public:
   VEOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 
   bool isToken() const override { return Kind == k_Token; }
   bool isReg() const override { return Kind == k_Register; }
   bool isImm() const override { return Kind == k_Immediate; }
bool isSImm7() {
 
     // Constant case
     if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
       int64_t Value = ConstExpr->getValue();
       return isInt<7>(Value);
     }
     return false;
   }
+  bool isMImm() const {
+    if (Kind != k_MImmOp)
+      return false;
+
+    // Constant case
+    if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {
+      int64_t Value = ConstExpr->getValue();
+      return isUInt<6>(Value);
+    }
+    return false;
+  }
 
   StringRef getToken() const {
     assert(Kind == k_Token && "Invalid access!");
     return StringRef(Tok.Data, Tok.Length);
   }
 
   unsigned getReg() const override {
     assert((Kind == k_Register) && "Invalid access!");
public:
 
   void setMemOffset(const MCExpr *off) {
     assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
             Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm) &&
            "Invalid access!");
     Mem.Offset = off;
   }
 
+  const MCExpr *getMImmVal() const {
+    assert((Kind == k_MImmOp) && "Invalid access!");
+    return MImm.Val;
+  }
+  bool getM0Flag() const {
+    assert((Kind == k_MImmOp) && "Invalid access!");
+    return MImm.M0Flag;
+  }
+
   /// getStartLoc - Get the location of the first token of this operand.
   SMLoc getStartLoc() const override { return StartLoc; }
   /// getEndLoc - Get the location of the last token of this operand.
   SMLoc getEndLoc() const override { return EndLoc; }
 
   void print(raw_ostream &OS) const override {
     switch (Kind) {
     case k_Token:
void print(raw_ostream &OS) const override {
     case k_MemoryZeroRegImm:
       assert(getMemOffset() != nullptr);
       OS << "Mem: 0+#" << getMemIndexReg() << "+" << *getMemOffset() << "\n";
       break;
     case k_MemoryZeroImmImm:
       assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
       OS << "Mem: 0+" << *getMemIndex() << "+" << *getMemOffset() << "\n";
       break;
+    case k_MImmOp:
+      OS << "MImm: (" << getMImmVal() << (getM0Flag() ? ")0" : ")1") << "\n";
+      break;
     }
   }
 
   void addRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getReg()));
   }
 
public:
   void addMEMriOperands(MCInst &Inst, unsigned N) const {
     // FIXME: implement
   }
 
   void addMEMziOperands(MCInst &Inst, unsigned N) const {
     // FIXME: implement
   }
 
+  void addMImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const auto *ConstExpr = dyn_cast<MCConstantExpr>(getMImmVal());
+    assert(ConstExpr && "Null operands!");
+    int64_t Value = ConstExpr->getValue();
+    if (getM0Flag())
+      Value += 64;
+    Inst.addOperand(MCOperand::createImm(Value));
+  }
+
   static std::unique_ptr<VEOperand> CreateToken(StringRef Str, SMLoc S) {
     auto Op = std::make_unique<VEOperand>(k_Token);
     Op->Tok.Data = Str.data();
     Op->Tok.Length = Str.size();
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
static std::unique_ptr<VEOperand> CreateImm(const MCExpr *Val, SMLoc S,
                                               SMLoc E) {
     auto Op = std::make_unique<VEOperand>(k_Immediate);
     Op->Imm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
+  static std::unique_ptr<VEOperand> CreateMImm(const MCExpr *Val, bool Flag,
+                                               SMLoc S, SMLoc E) {
+    auto Op = std::make_unique<VEOperand>(k_MImmOp);
+    Op->MImm.Val = Val;
+    Op->MImm.M0Flag = Flag;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
   static bool MorphToI32Reg(VEOperand &Op) {
     unsigned Reg = Op.getReg();
     unsigned regIdx = Reg - VE::SX0;
     if (regIdx > 63)
       return false;
     Op.Reg.RegNum = I32Regs[regIdx];
     return true;
   }
OperandMatchResultTy VEAsmParser::parseMEMOperand(OperandVector &Operands) {
   Operands.push_back(
       IndexValue
           ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset))
           : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset)));
 
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy VEAsmParser::parseMImmOperand(OperandVector &Operands) {
+  LLVM_DEBUG(dbgs() << "parseMImmOperand\n");
+
+  // Parsing "(" + number + ")0/1"
+  const AsmToken Tok1 = Parser.getTok();
+  if (!Tok1.is(AsmToken::LParen))
+    return MatchOperand_NoMatch;
+
+  Parser.Lex(); // Eat the '('.
+
+  const AsmToken Tok2 = Parser.getTok();
+  SMLoc E;
+  const MCExpr *EVal;
+  if (!Tok2.is(AsmToken::Integer) || getParser().parseExpression(EVal, E)) {
+    getLexer().UnLex(Tok1);
+    return MatchOperand_NoMatch;
+  }
+
+  const AsmToken Tok3 = Parser.getTok();
+  if (!Tok3.is(AsmToken::RParen)) {
+    getLexer().UnLex(Tok2);
+    getLexer().UnLex(Tok1);
+    return MatchOperand_NoMatch;
+  }
+  Parser.Lex(); // Eat the ')'.
+
+  const AsmToken &Tok4 = Parser.getTok();
+  StringRef Suffix = Tok4.getString();
+  if (Suffix != "1" && Suffix != "0") {
+    getLexer().UnLex(Tok3);
+    getLexer().UnLex(Tok2);
+    getLexer().UnLex(Tok1);
+    return MatchOperand_NoMatch;
+  }
+  Parser.Lex(); // Eat the value.
+  SMLoc EndLoc = SMLoc::getFromPointer(Suffix.end());
+  Operands.push_back(
+      VEOperand::CreateMImm(EVal, Suffix == "0", Tok1.getLoc(), EndLoc));
+  return MatchOperand_Success;
+}
+
 OperandMatchResultTy VEAsmParser::parseOperand(OperandVector &Operands,
                                                StringRef Mnemonic) {
   LLVM_DEBUG(dbgs() << "parseOperand\n");
   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
 
   // If there wasn't a custom match, try the generic matcher below. Otherwise,
   // there was a match, but an error occurred, in which case, just return that
   // the operand parsing failed.

llvm/lib/Target/VE/VEInstrInfo.td

 def uimm6 : Operand<i32>, PatLeaf<(imm), [{
     return isUInt<6>(N->getZExtValue()); }]>;
 
 // uimm7 - Generic immediate value.
 def uimm7 : Operand<i32>, PatLeaf<(imm), [{
     return isUInt<7>(N->getZExtValue()); }]>;
 
 // simm7 - Generic immediate value.
+def SImm7AsmOperand : AsmOperandClass {
+  let Name = "SImm7";
+}
 def simm7 : Operand<i32>, PatLeaf<(imm), [{
     return isInt<7>(N->getSExtValue()); }], LO7> {
+  let ParserMatchClass = SImm7AsmOperand;
   let DecoderMethod = "DecodeSIMM7";
 }
 
 // mimm - Special immediate value of sequential bit stream of 0 or 1.
+def MImmAsmOperand : AsmOperandClass {
+  let Name = "MImm";
+  let ParserMethod = "parseMImmOperand";
+}
 def mimm : Operand<i32>, PatLeaf<(imm), [{
     return isMImmVal(getImmVal(N)); }], MIMM> {
+  let ParserMatchClass = MImmAsmOperand;
   let PrintMethod = "printMImmOperand";
 }
 
 // simm7fp - Generic fp immediate value.
 def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{
     return isInt<7>(getFpImmVal(N));
   }], LO7FP> {
   let DecoderMethod = "DecodeSIMM7";

 // Section 8.4.8 - MPS (Multiply Single)
 defm MULSWSX : RRm<"muls.w.sx", 0x4B, I32, i32, mul>;
 let cx = 1 in defm MULSWZX : RRm<"muls.w.zx", 0x4B, I32, i32>;
 
 // Section 8.4.9 - MPX (Multiply)
 defm MULSL : RRm<"muls.l", 0x6E, I64, i64, mul>;
 
 // Section 8.4.10 - MPD (Multiply)
+defm MULSLW : RRbm<"muls.l.w", 0x6B, I64, i64, I32, i32>;
 
 // Section 8.4.11 - DIV (Divide)
 defm DIVUL : RRNCm<"divu.l", 0x6F, I64, i64, udiv>;
 let cx = 1 in defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>;
 
 // Section 8.4.12 - DVS (Divide Single)
 defm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;
 let cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>;

llvm/test/MC/VE/ADD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: addu.l %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x48]
+addu.l %s11, %s20, %s22
+
+# CHECK-INST: addu.w %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x48]
+addu.w %s11, 22, %s22
+
+# CHECK-INST: adds.w.sx %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x4a]
+adds.w.sx %s11, 63, (60)1
+
+# CHECK-INST: adds.w.zx %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x40,0x8b,0x4a]
+adds.w.zx %s11, -64, %s22
+
+# CHECK-INST: adds.l %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x59]
+adds.l %s11, -64, (22)0

llvm/test/MC/VE/CMP.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cmpu.l %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x55]
+cmpu.l %s11, %s20, %s22
+
+# CHECK-INST: cmpu.w %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x55]
+cmpu.w %s11, 22, %s22
+
+# CHECK-INST: cmps.w.sx %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x7a]
+cmps.w.sx %s11, 63, (60)1
+
+# CHECK-INST: cmps.w.zx %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x40,0x8b,0x7a]
+cmps.w.zx %s11, -64, %s22
+
+# CHECK-INST: cmps.l %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x6a]
+cmps.l %s11, -64, (22)0

llvm/test/MC/VE/DIV.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: divu.l %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x6f]
+divu.l %s11, %s20, %s22
+
+# CHECK-INST: divu.w %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x6f]
+divu.w %s11, 22, %s22
+
+# CHECK-INST: divs.w.sx %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x7b]
+divs.w.sx %s11, 63, (60)1
+
+# CHECK-INST: divs.w.zx %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x40,0x8b,0x7b]
+divs.w.zx %s11, -64, %s22
+
+# CHECK-INST: divs.l %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x7f]
+divs.l %s11, -64, (22)0

llvm/test/MC/VE/MAXMIN.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: maxs.w.sx %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x78]
+maxs.w.sx %s11, %s20, %s22
+
+# CHECK-INST: maxs.w.zx %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x78]
+maxs.w.zx %s11, 22, %s22
+
+# CHECK-INST: mins.w.sx %s11, 63, (63)1
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x3f,0x3f,0x0b,0x78]
+mins.w.sx %s11, 63, (63)1
+
+# CHECK-INST: mins.w.zx %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x96,0x40,0x8b,0x78]
+mins.w.zx %s11, -64, %s22
+
+# CHECK-INST: maxs.l %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x68]
+maxs.l %s11, -64, (22)0
+
+# CHECK-INST: mins.l %s11, -64, (22)1
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x16,0x40,0x0b,0x68]
+mins.l %s11, -64, (22)1

llvm/test/MC/VE/MUL.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: mulu.l %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x49]
+mulu.l %s11, %s20, %s22
+
+# CHECK-INST: mulu.w %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x49]
+mulu.w %s11, 22, %s22
+
+# CHECK-INST: muls.w.sx %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x4b]
+muls.w.sx %s11, 63, (60)1
+
+# CHECK-INST: muls.w.zx %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x40,0x8b,0x4b]
+muls.w.zx %s11, -64, %s22
+
+# CHECK-INST: muls.l %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x6e]
+muls.l %s11, -64, (22)0
+
+# CHECK-INST: muls.l.w %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x6b]
+muls.l.w %s11, -64, (22)0

llvm/test/MC/VE/SUB.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: subu.l %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x58]
+subu.l %s11, %s20, %s22
+
+# CHECK-INST: subu.w %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x58]
+subu.w %s11, 22, %s22
+
+# CHECK-INST: subs.w.sx %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x5a]
+subs.w.sx %s11, 63, (60)1
+
+# CHECK-INST: subs.w.zx %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x40,0x8b,0x5a]
+subs.w.zx %s11, -64, %s22
+
+# CHECK-INST: subs.l %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x0b,0x5b]
+subs.l %s11, -64, (22)0