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[VE] Support logical operation instructions in MC layer
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Authored by kaz7 on Jun 4 2020, 8:36 PM.

Details

Summary

Add regression tests of asmparser, mccodeemitter, and disassembler for
logical operation instructions. Also change asmparser to support CMOV
instruction. And, add new EQV/MRG/NND isntructions also.

Depends on D81215.

Diff Detail

Event Timeline

kaz7 created this revision.Jun 4 2020, 8:36 PM
simoll added a comment.Jun 5 2020, 1:42 AM

LGTM with one style nit.

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
694

Redundant ?:

kaz7 marked an inline comment as done.Jun 5 2020, 2:23 AM
kaz7 added inline comments.
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
694

Will modify it. Thanks!

kaz7 planned changes to this revision.Jun 5 2020, 2:28 AM
kaz7 updated this revision to Diff 268778.Jun 5 2020, 6:42 AM

Updated following a suggestion.

simoll accepted this revision.Jun 5 2020, 7:44 AM
This revision is now accepted and ready to land.Jun 5 2020, 7:44 AM
This revision was automatically updated to reflect the committed changes.