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Differential D80922

GlobalISel: Infer nofpexcept flag during selection for non-strict ops
ClosedPublic

Authored by arsenm on Jun 1 2020, 6:16 AM.

Details

Reviewers
paquette
aemerson
aditya_nandakumar
dsanders
Summary

Match SelectionDAG's behavior of adding nofpexcept to out instructions
that may raise fp exceptions that are selected from instructions that
do not.

Diff Detail

Event Timeline

arsenm created this revision.Jun 1 2020, 6:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 1 2020, 6:16 AM
Herald added subscribers: kerbowa, rovka, nhaehnle and 2 others. · View Herald Transcript
paquette accepted this revision.Jun 5 2020, 9:34 AM

LGTM

This revision is now accepted and ready to land.Jun 5 2020, 9:34 AM
arsenm closed this revision.Jun 5 2020, 11:00 AM

3b5d4aa258a0f7ccbd5c3ade4286dca8f5d2d984

Revision Contents

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llvm/
CodeGen/
GlobalISel/
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X86/
GlobalISel/
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Diff 267595

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
&ISelInfo, &ISelInfo,
const int64_t *MatchTable, const TargetInstrInfo &TII, const int64_t *MatchTable, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
CodeGenCoverage &CoverageInfo) const { CodeGenCoverage &CoverageInfo) const {
uint64_t CurrentIdx = 0; uint64_t CurrentIdx = 0;
SmallVector<uint64_t, 4> OnFailResumeAt; SmallVector<uint64_t, 4> OnFailResumeAt;
uint16_t Flags = State.MIs[0]->getFlags();
// Bypass the flag check on the instruction, and only look at the MCInstrDesc.
bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
const uint16_t Flags = State.MIs[0]->getFlags();
enum RejectAction { RejectAndGiveUp, RejectAndResume }; enum RejectAction { RejectAndGiveUp, RejectAndResume };
auto handleReject = [&]() -> RejectAction { auto handleReject = [&]() -> RejectAction {
DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
dbgs() << CurrentIdx << ": Rejected\n"); dbgs() << CurrentIdx << ": Rejected\n");
if (OnFailResumeAt.empty()) if (OnFailResumeAt.empty())
return RejectAndGiveUp; return RejectAndGiveUp;
CurrentIdx = OnFailResumeAt.pop_back_val(); CurrentIdx = OnFailResumeAt.pop_back_val();
DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " (" dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
<< OnFailResumeAt.size() << " try-blocks remain)\n"); << OnFailResumeAt.size() << " try-blocks remain)\n");
return RejectAndResume; return RejectAndResume;
}; };
auto propagateFlags = [&](NewMIVector &OutMIs) { auto propagateFlags = [=](NewMIVector &OutMIs) {
if (Flags == MachineInstr::MIFlag::NoFlags) for (auto MIB : OutMIs) {
return false; // Set the NoFPExcept flag when no original matched instruction could
for (auto MIB : OutMIs) // raise an FP exception, but the new instruction potentially might.
MIB.setMIFlags(Flags); uint16_t MIBFlags = Flags;
if (NoFPException && MIB->mayRaiseFPException())
MIBFlags |= MachineInstr::NoFPExcept;
MIB.setMIFlags(MIBFlags);
}
return true; return true;
}; };
while (true) { while (true) {
assert(CurrentIdx != ~0u && "Invalid MatchTable index"); assert(CurrentIdx != ~0u && "Invalid MatchTable index");
int64_t MatcherOpcode = MatchTable[CurrentIdx++]; int64_t MatcherOpcode = MatchTable[CurrentIdx++];
switch (MatcherOpcode) { switch (MatcherOpcode) {
▲ Show 20 Lines • Show All 1,002 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: cos_s32_vs ; CHECK-LABEL: name: cos_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: cos_s32_vv name: cos_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cos_s32_vv ; CHECK-LABEL: name: cos_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1:sgpr(s16) (in function: cos_s16_vs) # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1:sgpr(s16) (in function: cos_s16_vs)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1:vgpr(s16) (in function: cos_s16_vv) # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1:vgpr(s16) (in function: cos_s16_vv)
---
name: cos_s16_vs name: cos_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: cos_s16_vs ; CHECK-LABEL: name: cos_s16_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: cos_s16_vv name: cos_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cos_s16_vv ; CHECK-LABEL: name: cos_s16_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pkrtz_vsv ; GCN-LABEL: name: cvt_pkrtz_vsv
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: cvt_pkrtz_vvs name: cvt_pkrtz_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pkrtz_vvs ; GCN-LABEL: name: cvt_pkrtz_vvs
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: cvt_pkrtz_vvv name: cvt_pkrtz_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: cvt_pkrtz_vvv ; GCN-LABEL: name: cvt_pkrtz_vvv
; GCN: liveins: $vgpr0, $vgpr1 ; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir

Show All 15 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GCN-LABEL: name: fmed3_s16_vvvv ; GCN-LABEL: name: fmed3_s16_vvvv
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]] ; GCN: S_ENDPGM 0, implicit %6
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s16) = G_TRUNC %0 %3:vgpr(s16) = G_TRUNC %0
%4:vgpr(s16) = G_TRUNC %1 %4:vgpr(s16) = G_TRUNC %1
%5:vgpr(s16) = G_TRUNC %2 %5:vgpr(s16) = G_TRUNC %2
%6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5 %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
Show All 9 Linesbody: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1 liveins: $sgpr0, $vgpr0, $vgpr1
; GCN-LABEL: name: fmed3_s16_vsvv ; GCN-LABEL: name: fmed3_s16_vsvv
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GCN: %6:vgpr_32 = nofpexcept V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]] ; GCN: S_ENDPGM 0, implicit %6
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:sgpr(s16) = G_TRUNC %0 %3:sgpr(s16) = G_TRUNC %0
%4:vgpr(s16) = G_TRUNC %1 %4:vgpr(s16) = G_TRUNC %1
%5:vgpr(s16) = G_TRUNC %2 %5:vgpr(s16) = G_TRUNC %2
%6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5 %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: fract_s32_vs ; CHECK-LABEL: name: fract_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fract_s32_vv name: fract_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fract_s32_vv ; CHECK-LABEL: name: fract_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fract_s64_vs name: fract_s64_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fract_s64_vs ; CHECK-LABEL: name: fract_s64_vs
; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: liveins: $sgpr0_sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fract_s64_vv name: fract_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fract_s64_vv ; CHECK-LABEL: name: fract_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir

Show All 13 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: fract_s16_vs ; CHECK-LABEL: name: fract_s16_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fract_s16_vv name: fract_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fract_s16_vv ; CHECK-LABEL: name: fract_s16_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
--- ---
name: ldexp_s32_vsv name: ldexp_s32_vsv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: ldexp_s32_vsv ; GCN-LABEL: name: ldexp_s32_vsv
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ldexp_s32_vvs name: ldexp_s32_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: ldexp_s32_vvs ; GCN-LABEL: name: ldexp_s32_vvs
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ldexp_s32_vvv name: ldexp_s32_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: ldexp_s32_vvv ; GCN-LABEL: name: ldexp_s32_vvv
; GCN: liveins: $vgpr0, $vgpr1 ; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ldexp_s64_vsv name: ldexp_s64_vsv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
; GCN-LABEL: name: ldexp_s64_vsv ; GCN-LABEL: name: ldexp_s64_vsv
; GCN: liveins: $sgpr0_sgpr1, $vgpr0 ; GCN: liveins: $sgpr0_sgpr1, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vreg_64 = nofpexcept V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1 %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ldexp_s64_vvs name: ldexp_s64_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0 liveins: $sgpr0_sgpr1, $vgpr0
; GCN-LABEL: name: ldexp_s64_vvs ; GCN-LABEL: name: ldexp_s64_vvs
; GCN: liveins: $sgpr0_sgpr1, $vgpr0 ; GCN: liveins: $sgpr0_sgpr1, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vreg_64 = nofpexcept V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1 %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ldexp_s64_vvv name: ldexp_s64_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2 liveins: $vgpr0_vgpr1, $vgpr2
; GCN-LABEL: name: ldexp_s64_vvv ; GCN-LABEL: name: ldexp_s64_vvv
; GCN: liveins: $vgpr0_vgpr1, $vgpr2 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vreg_64 = nofpexcept V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]] ; GCN: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2 %1:vgpr(s32) = COPY $vgpr2
%2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1 %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir

Show All 13 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: ldexp_s16_vsv ; GCN-LABEL: name: ldexp_s16_vsv
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]] ; GCN: S_ENDPGM 0, implicit %3
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s16) = G_TRUNC %0 %2:sgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1 %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: ldexp_s16_vvs name: ldexp_s16_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: ldexp_s16_vvs ; GCN-LABEL: name: ldexp_s16_vvs
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]] ; GCN: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1 %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: ldexp_s16_vvv name: ldexp_s16_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: ldexp_s16_vvv ; GCN-LABEL: name: ldexp_s16_vvv
; GCN: liveins: $vgpr0, $vgpr1 ; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]] ; GCN: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1 %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir

Show All 14 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rcp_legacy_s32_vs ; CHECK-LABEL: name: rcp_legacy_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rcp_legacy_s32_vv name: rcp_legacy_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rcp_legacy_s32_vv ; CHECK-LABEL: name: rcp_legacy_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rcp_s32_vs ; CHECK-LABEL: name: rcp_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rcp_s32_vv name: rcp_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rcp_s32_vv ; CHECK-LABEL: name: rcp_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rcp_s64_vs name: rcp_s64_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: rcp_s64_vs ; CHECK-LABEL: name: rcp_s64_vs
; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: liveins: $sgpr0_sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rcp_s64_vv name: rcp_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: rcp_s64_vv ; CHECK-LABEL: name: rcp_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir

Show All 12 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rcp_s16_vs ; CHECK-LABEL: name: rcp_s16_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: rcp_s16_vv name: rcp_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rcp_s16_vv ; CHECK-LABEL: name: rcp_s16_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir

Show All 14 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rsq_clamp_s32_vs ; CHECK-LABEL: name: rsq_clamp_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rsq_clamp_s32_vv name: rsq_clamp_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rsq_clamp_s32_vv ; CHECK-LABEL: name: rsq_clamp_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir

Show All 14 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rsq_legacy_s32_vs ; CHECK-LABEL: name: rsq_legacy_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rsq_legacy_s32_vv name: rsq_legacy_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rsq_legacy_s32_vv ; CHECK-LABEL: name: rsq_legacy_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rsq_s32_vs ; CHECK-LABEL: name: rsq_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rsq_s32_vv name: rsq_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rsq_s32_vv ; CHECK-LABEL: name: rsq_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rsq_s64_vs name: rsq_s64_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: rsq_s64_vs ; CHECK-LABEL: name: rsq_s64_vs
; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: liveins: $sgpr0_sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: rsq_s64_vv name: rsq_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: rsq_s64_vv ; CHECK-LABEL: name: rsq_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1:sgpr(s16) (in function: rsq_s16_vs) # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1:sgpr(s16) (in function: rsq_s16_vs)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1:vgpr(s16) (in function: rsq_s16_vv) # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1:vgpr(s16) (in function: rsq_s16_vv)
---
name: rsq_s16_vs name: rsq_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: rsq_s16_vs ; CHECK-LABEL: name: rsq_s16_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: rsq_s16_vv name: rsq_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: rsq_s16_vv ; CHECK-LABEL: name: rsq_s16_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: sin_s32_vs ; CHECK-LABEL: name: sin_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: sin_s32_vv name: sin_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: sin_s32_vv ; CHECK-LABEL: name: sin_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:sgpr(s16) (in function: sin_s16_vs) # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:sgpr(s16) (in function: sin_s16_vs)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:vgpr(s16) (in function: sin_s16_vv) # SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:vgpr(s16) (in function: sin_s16_vv)
---
name: sin_s16_vs name: sin_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: sin_s16_vs ; CHECK-LABEL: name: sin_s16_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: sin_s16_vv name: sin_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: sin_s16_vv ; CHECK-LABEL: name: sin_s16_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
--- ---
name: fadd_s16_vvv name: fadd_s16_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: fadd_s16_vvv ; GFX8-LABEL: name: fadd_s16_vvv
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %4:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FADD %2, %3 %4:vgpr(s16) = G_FADD %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fadd_s16_vsv name: fadd_s16_vsv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX8-LABEL: name: fadd_s16_vsv ; GFX8-LABEL: name: fadd_s16_vsv
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %4:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %4
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s16) = G_TRUNC %0 %2:sgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FADD %2, %3 %4:vgpr(s16) = G_FADD %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fadd_s16_vvs name: fadd_s16_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX8-LABEL: name: fadd_s16_vvs ; GFX8-LABEL: name: fadd_s16_vvs
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %4:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:sgpr(s16) = G_TRUNC %1 %3:sgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FADD %2, %3 %4:vgpr(s16) = G_FADD %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fadd_s16_vvv_fabs_lhs name: fadd_s16_vvv_fabs_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs ; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %5:vgpr_32 = nofpexcept V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FABS %2 %4:vgpr(s16) = G_FABS %2
%5:vgpr(s16) = G_FADD %4, %3 %5:vgpr(s16) = G_FADD %4, %3
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...
--- ---
name: fadd_s16_vvv_fabs_rhs name: fadd_s16_vvv_fabs_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs ; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %5:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FABS %3 %4:vgpr(s16) = G_FABS %3
%5:vgpr(s16) = G_FADD %2, %4 %5:vgpr(s16) = G_FADD %2, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...
--- ---
name: fadd_s16_vvv_fneg_fabs_lhs name: fadd_s16_vvv_fneg_fabs_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %6:vgpr_32 = nofpexcept V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %6
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FABS %2 %4:vgpr(s16) = G_FABS %2
%5:vgpr(s16) = G_FNEG %4 %5:vgpr(s16) = G_FNEG %4
%6:vgpr(s16) = G_FADD %5, %3 %6:vgpr(s16) = G_FADD %5, %3
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
... ...
--- ---
name: fadd_s16_vvv_fneg_fabs_rhs name: fadd_s16_vvv_fneg_fabs_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %6:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %6
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FABS %3 %4:vgpr(s16) = G_FABS %3
%5:vgpr(s16) = G_FNEG %4 %5:vgpr(s16) = G_FNEG %4
%6:vgpr(s16) = G_FADD %2, %5 %6:vgpr(s16) = G_FADD %2, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
... ...
--- ---
name: fadd_s16_fneg_copy_sgpr name: fadd_s16_fneg_copy_sgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr ; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX8: %5:vgpr_32 = nofpexcept V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:sgpr(s16) = G_TRUNC %1 %3:sgpr(s16) = G_TRUNC %1
%4:sgpr(s16) = G_FNEG %3 %4:sgpr(s16) = G_FNEG %3
%5:vgpr(s16) = G_FADD %2, %4 %5:vgpr(s16) = G_FADD %2, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
--- ---
name: fadd_s32_vvv name: fadd_s32_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv ; GFX6-LABEL: name: fadd_s32_vvv
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FADD %0, %1 %2:vgpr(s32) = G_FADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fadd_s32_vsv name: fadd_s32_vsv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_vsv ; GFX6-LABEL: name: fadd_s32_vsv
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_FADD %0, %1 %2:vgpr(s32) = G_FADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fadd_s32_vvs name: fadd_s32_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_vvs ; GFX6-LABEL: name: fadd_s32_vvs
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = G_FADD %0, %1 %2:vgpr(s32) = G_FADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fadd_s32_vvv_fabs_lhs name: fadd_s32_vvv_fabs_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs ; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %0 %2:vgpr(s32) = G_FABS %0
%3:vgpr(s32) = G_FADD %2, %1 %3:vgpr(s32) = G_FADD %2, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fadd_s32_vvv_fabs_rhs name: fadd_s32_vvv_fabs_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs ; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX6: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %1 %2:vgpr(s32) = G_FABS %1
%3:vgpr(s32) = G_FADD %1, %2 %3:vgpr(s32) = G_FADD %1, %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fadd_s32_vvv_fneg_fabs_lhs name: fadd_s32_vvv_fneg_fabs_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %0 %2:vgpr(s32) = G_FABS %0
%3:vgpr(s32) = G_FNEG %2 %3:vgpr(s32) = G_FNEG %2
%4:vgpr(s32) = G_FADD %3, %1 %4:vgpr(s32) = G_FADD %3, %1
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fadd_s32_vvv_fneg_fabs_rhs name: fadd_s32_vvv_fneg_fabs_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %1 %2:vgpr(s32) = G_FABS %1
%3:vgpr(s32) = G_FNEG %2 %3:vgpr(s32) = G_FNEG %2
%4:vgpr(s32) = G_FADD %1, %3 %4:vgpr(s32) = G_FADD %1, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
# Need to look through reg bank copy to find source modifiers # Need to look through reg bank copy to find source modifiers
--- ---
name: fadd_s32_fneg_copy_sgpr name: fadd_s32_fneg_copy_sgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:sgpr(s32) = G_FNEG %1 %2:sgpr(s32) = G_FNEG %1
%3:vgpr(s32) = COPY %2 %3:vgpr(s32) = COPY %2
%4:vgpr(s32) = G_FADD %0, %3 %4:vgpr(s32) = G_FADD %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
# Need to look through copy in between fneg and fabs # Need to look through copy in between fneg and fabs
--- ---
name: fadd_s32_copy_fneg_copy_fabs name: fadd_s32_copy_fneg_copy_fabs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $sgpr0 liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %6
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:sgpr(s32) = G_FABS %1 %2:sgpr(s32) = G_FABS %1
%3:sgpr(s32) = COPY %2 %3:sgpr(s32) = COPY %2
%4:sgpr(s32) = G_FNEG %3 %4:sgpr(s32) = G_FNEG %3
%5:sgpr(s32) = COPY %4 %5:sgpr(s32) = COPY %4
%6:vgpr(s32) = G_FADD %0, %5 %6:vgpr(s32) = G_FADD %0, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
Show All 13 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr ; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec ; GFX6: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %6
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FABS %0 %2:sgpr(s32) = G_FABS %0
%3:sgpr(s32) = G_FABS %1 %3:sgpr(s32) = G_FABS %1
%4:vgpr(s32) = COPY %2 %4:vgpr(s32) = COPY %2
%5:vgpr(s32) = COPY %3 %5:vgpr(s32) = COPY %3
%6:vgpr(s32) = G_FADD %4, %5 %6:vgpr(s32) = G_FADD %4, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr ; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec ; GFX6: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %6
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FNEG %0 %2:sgpr(s32) = G_FNEG %0
%3:sgpr(s32) = G_FNEG %1 %3:sgpr(s32) = G_FNEG %1
%4:vgpr(s32) = COPY %2 %4:vgpr(s32) = COPY %2
%5:vgpr(s32) = COPY %3 %5:vgpr(s32) = COPY %3
%6:vgpr(s32) = G_FADD %4, %5 %6:vgpr(s32) = G_FADD %4, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr ; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec ; GFX6: %8:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]] ; GFX6: S_ENDPGM 0, implicit %8
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FABS %0 %2:sgpr(s32) = G_FABS %0
%3:sgpr(s32) = G_FABS %1 %3:sgpr(s32) = G_FABS %1
%4:sgpr(s32) = G_FNEG %2 %4:sgpr(s32) = G_FNEG %2
%5:sgpr(s32) = G_FNEG %3 %5:sgpr(s32) = G_FNEG %3
%6:vgpr(s32) = COPY %4 %6:vgpr(s32) = COPY %4
%7:vgpr(s32) = COPY %5 %7:vgpr(s32) = COPY %5
%8:vgpr(s32) = G_FADD %6, %7 %8:vgpr(s32) = G_FADD %6, %7
S_ENDPGM 0, implicit %8 S_ENDPGM 0, implicit %8
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
--- ---
name: fadd_s64_vvv name: fadd_s64_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: fadd_s64_vvv ; GFX6-LABEL: name: fadd_s64_vvv
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %2:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_FADD %0, %1 %2:vgpr(s64) = G_FADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fadd_s64_vsv name: fadd_s64_vsv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GFX6-LABEL: name: fadd_s64_vsv ; GFX6-LABEL: name: fadd_s64_vsv
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %2:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %2
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr0_vgpr1 %1:vgpr(s64) = COPY $vgpr0_vgpr1
%2:vgpr(s64) = G_FADD %0, %1 %2:vgpr(s64) = G_FADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fadd_s64_vvs name: fadd_s64_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GFX6-LABEL: name: fadd_s64_vvs ; GFX6-LABEL: name: fadd_s64_vvs
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %2:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s64) = COPY $sgpr0_sgpr1 %1:sgpr(s64) = COPY $sgpr0_sgpr1
%2:vgpr(s64) = G_FADD %0, %1 %2:vgpr(s64) = G_FADD %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fadd_s64_vvv_fabs_lhs name: fadd_s64_vvv_fabs_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: fadd_s64_vvv_fabs_lhs ; GFX6-LABEL: name: fadd_s64_vvv_fabs_lhs
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %3:vreg_64 = nofpexcept V_ADD_F64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %3
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_FABS %0 %2:vgpr(s64) = G_FABS %0
%3:vgpr(s64) = G_FADD %2, %1 %3:vgpr(s64) = G_FADD %2, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fadd_s64_vvv_fabs_rhs name: fadd_s64_vvv_fabs_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: fadd_s64_vvv_fabs_rhs ; GFX6-LABEL: name: fadd_s64_vvv_fabs_rhs
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX6: %3:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %3
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_FABS %1 %2:vgpr(s64) = G_FABS %1
%3:vgpr(s64) = G_FADD %1, %2 %3:vgpr(s64) = G_FADD %1, %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fadd_s64_vvv_fneg_fabs_lhs name: fadd_s64_vvv_fneg_fabs_lhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_lhs ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_lhs
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vreg_64 = nofpexcept V_ADD_F64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %4
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_FABS %0 %2:vgpr(s64) = G_FABS %0
%3:vgpr(s64) = G_FNEG %2 %3:vgpr(s64) = G_FNEG %2
%4:vgpr(s64) = G_FADD %3, %1 %4:vgpr(s64) = G_FADD %3, %1
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fadd_s64_vvv_fneg_fabs_rhs name: fadd_s64_vvv_fneg_fabs_rhs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_rhs ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_rhs
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %4
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr0_vgpr1 %1:vgpr(s64) = COPY $vgpr0_vgpr1
%2:vgpr(s64) = G_FABS %1 %2:vgpr(s64) = G_FABS %1
%3:vgpr(s64) = G_FNEG %2 %3:vgpr(s64) = G_FNEG %2
%4:vgpr(s64) = G_FADD %1, %3 %4:vgpr(s64) = G_FADD %1, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
# Need to look through reg bank copy to find source modifiers # Need to look through reg bank copy to find source modifiers
--- ---
name: fadd_s64_fneg_copy_sgpr name: fadd_s64_fneg_copy_sgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr ; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY1]] ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %4
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s64) = COPY $sgpr0_sgpr1 %1:sgpr(s64) = COPY $sgpr0_sgpr1
%2:sgpr(s64) = G_FNEG %1 %2:sgpr(s64) = G_FNEG %1
%3:vgpr(s64) = COPY %2 %3:vgpr(s64) = COPY %2
%4:vgpr(s64) = G_FADD %0, %3 %4:vgpr(s64) = G_FADD %0, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 11 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
; GFX6-LABEL: name: fadd_s64_copy_fabs_sgpr_copy_fabs_sgpr ; GFX6-LABEL: name: fadd_s64_copy_fabs_sgpr_copy_fabs_sgpr
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]] ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]] ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec ; GFX6: %6:vreg_64 = nofpexcept V_ADD_F64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %6
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = COPY $sgpr2_sgpr3 %1:sgpr(s64) = COPY $sgpr2_sgpr3
%2:sgpr(s64) = G_FABS %0 %2:sgpr(s64) = G_FABS %0
%3:sgpr(s64) = G_FABS %1 %3:sgpr(s64) = G_FABS %1
%4:vgpr(s64) = COPY %2 %4:vgpr(s64) = COPY %2
%5:vgpr(s64) = COPY %3 %5:vgpr(s64) = COPY %3
%6:vgpr(s64) = G_FADD %4, %5 %6:vgpr(s64) = G_FADD %4, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s64_copy_fneg_sgpr_copy_fneg_sgpr ; GFX6-LABEL: name: fadd_s64_copy_fneg_sgpr_copy_fneg_sgpr
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]] ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]] ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec ; GFX6: %6:vreg_64 = nofpexcept V_ADD_F64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %6
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = COPY $sgpr2_sgpr3 %1:sgpr(s64) = COPY $sgpr2_sgpr3
%2:sgpr(s64) = G_FNEG %0 %2:sgpr(s64) = G_FNEG %0
%3:sgpr(s64) = G_FNEG %1 %3:sgpr(s64) = G_FNEG %1
%4:vgpr(s64) = COPY %2 %4:vgpr(s64) = COPY %2
%5:vgpr(s64) = COPY %3 %5:vgpr(s64) = COPY %3
%6:vgpr(s64) = G_FADD %4, %5 %6:vgpr(s64) = G_FADD %4, %5
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s64_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr ; GFX6-LABEL: name: fadd_s64_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]] ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]] ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec ; GFX6: %8:vreg_64 = nofpexcept V_ADD_F64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]] ; GFX6: S_ENDPGM 0, implicit %8
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = COPY $sgpr2_sgpr3 %1:sgpr(s64) = COPY $sgpr2_sgpr3
%2:sgpr(s64) = G_FABS %0 %2:sgpr(s64) = G_FABS %0
%3:sgpr(s64) = G_FABS %1 %3:sgpr(s64) = G_FABS %1
%4:sgpr(s64) = G_FNEG %2 %4:sgpr(s64) = G_FNEG %2
%5:sgpr(s64) = G_FNEG %3 %5:sgpr(s64) = G_FNEG %3
%6:vgpr(s64) = COPY %4 %6:vgpr(s64) = COPY %4
%7:vgpr(s64) = COPY %5 %7:vgpr(s64) = COPY %5
%8:vgpr(s64) = G_FADD %6, %7 %8:vgpr(s64) = G_FADD %6, %7
S_ENDPGM 0, implicit %8 S_ENDPGM 0, implicit %8
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir

Show All 11 Lines mode:
fp64-fp16-input-denormals: true fp64-fp16-input-denormals: true
fp64-fp16-output-denormals: true fp64-fp16-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_f16_denorm ; GFX8-LABEL: name: fcanonicalize_f16_denorm
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %2:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: fcanonicalize_f16_denorm ; GFX9-LABEL: name: fcanonicalize_f16_denorm
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FCANONICALIZE %1 %2:vgpr(s16) = G_FCANONICALIZE %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcanonicalize_f16_flush name: fcanonicalize_f16_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp64-fp16-input-denormals: false fp64-fp16-input-denormals: false
fp64-fp16-output-denormals: false fp64-fp16-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_f16_flush ; GFX8-LABEL: name: fcanonicalize_f16_flush
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, 15360, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %2:vgpr_32 = nofpexcept V_MUL_F16_e64 0, 15360, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]] ; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: fcanonicalize_f16_flush ; GFX9-LABEL: name: fcanonicalize_f16_flush
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FCANONICALIZE %1 %2:vgpr(s16) = G_FCANONICALIZE %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcanonicalize_f32_denorm name: fcanonicalize_f32_denorm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: true fp32-input-denormals: true
fp32-output-denormals: true fp32-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_f32_denorm ; GFX8-LABEL: name: fcanonicalize_f32_denorm
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %1:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %1
; GFX9-LABEL: name: fcanonicalize_f32_denorm ; GFX9-LABEL: name: fcanonicalize_f32_denorm
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %1:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FCANONICALIZE %0 %1:vgpr(s32) = G_FCANONICALIZE %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fcanonicalize_f32_flush name: fcanonicalize_f32_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: false fp32-input-denormals: false
fp32-output-denormals: false fp32-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_f32_flush ; GFX8-LABEL: name: fcanonicalize_f32_flush
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %1:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %1
; GFX9-LABEL: name: fcanonicalize_f32_flush ; GFX9-LABEL: name: fcanonicalize_f32_flush
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %1:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FCANONICALIZE %0 %1:vgpr(s32) = G_FCANONICALIZE %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fcanonicalize_v2f16_denorm name: fcanonicalize_v2f16_denorm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp64-fp16-input-denormals: true fp64-fp16-input-denormals: true
fp64-fp16-output-denormals: true fp64-fp16-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_v2f16_denorm ; GFX8-LABEL: name: fcanonicalize_v2f16_denorm
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX8: %1:vgpr_32 = nofpexcept V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]] ; GFX8: S_ENDPGM 0, implicit %1
; GFX9-LABEL: name: fcanonicalize_v2f16_denorm ; GFX9-LABEL: name: fcanonicalize_v2f16_denorm
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %1:vgpr_32 = nofpexcept V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]] ; GFX9: S_ENDPGM 0, implicit %1
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = G_FCANONICALIZE %0 %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fcanonicalize_v2f16_flush name: fcanonicalize_v2f16_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp64-fp16-input-denormals: false fp64-fp16-input-denormals: false
fp64-fp16-output-denormals: false fp64-fp16-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_v2f16_flush ; GFX8-LABEL: name: fcanonicalize_v2f16_flush
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 0, 15360, 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX8: %1:vgpr_32 = nofpexcept V_PK_MUL_F16 0, 15360, 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]] ; GFX8: S_ENDPGM 0, implicit %1
; GFX9-LABEL: name: fcanonicalize_v2f16_flush ; GFX9-LABEL: name: fcanonicalize_v2f16_flush
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %1:vgpr_32 = nofpexcept V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]] ; GFX9: S_ENDPGM 0, implicit %1
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = G_FCANONICALIZE %0 %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fcanonicalize_f64_denorm name: fcanonicalize_f64_denorm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp64-fp16-input-denormals: true fp64-fp16-input-denormals: true
fp64-fp16-output-denormals: true fp64-fp16-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX8-LABEL: name: fcanonicalize_f64_denorm ; GFX8-LABEL: name: fcanonicalize_f64_denorm
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX8: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %1:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MAX_F64_]] ; GFX8: S_ENDPGM 0, implicit %1
; GFX9-LABEL: name: fcanonicalize_f64_denorm ; GFX9-LABEL: name: fcanonicalize_f64_denorm
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %1:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]] ; GFX9: S_ENDPGM 0, implicit %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FCANONICALIZE %0 %1:vgpr(s64) = G_FCANONICALIZE %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fcanonicalize_f64_flush name: fcanonicalize_f64_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp64-fp16-input-denormals: false fp64-fp16-input-denormals: false
fp64-fp16-output-denormals: false fp64-fp16-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX8-LABEL: name: fcanonicalize_f64_flush ; GFX8-LABEL: name: fcanonicalize_f64_flush
; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX8: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, 4607182418800017408, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %1:vreg_64 = nofpexcept V_MUL_F64 0, 4607182418800017408, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F64_]] ; GFX8: S_ENDPGM 0, implicit %1
; GFX9-LABEL: name: fcanonicalize_f64_flush ; GFX9-LABEL: name: fcanonicalize_f64_flush
; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %1:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]] ; GFX9: S_ENDPGM 0, implicit %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FCANONICALIZE %0 %1:vgpr(s64) = G_FCANONICALIZE %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fcanonicalize_fabs_f32_denorm name: fcanonicalize_fabs_f32_denorm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: true fp32-input-denormals: true
fp32-output-denormals: true fp32-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_fabs_f32_denorm ; GFX8-LABEL: name: fcanonicalize_fabs_f32_denorm
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %2:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: fcanonicalize_fabs_f32_denorm ; GFX9-LABEL: name: fcanonicalize_fabs_f32_denorm
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FABS %0 %1:vgpr(s32) = G_FABS %0
%2:vgpr(s32) = G_FCANONICALIZE %1 %2:vgpr(s32) = G_FCANONICALIZE %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcanonicalize_fabs_f32_flush name: fcanonicalize_fabs_f32_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: false fp32-input-denormals: false
fp32-output-denormals: false fp32-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_fabs_f32_flush ; GFX8-LABEL: name: fcanonicalize_fabs_f32_flush
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %2:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: fcanonicalize_fabs_f32_flush ; GFX9-LABEL: name: fcanonicalize_fabs_f32_flush
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FABS %0 %1:vgpr(s32) = G_FABS %0
%2:vgpr(s32) = G_FCANONICALIZE %1 %2:vgpr(s32) = G_FCANONICALIZE %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcanonicalize_fneg_f32_denorm name: fcanonicalize_fneg_f32_denorm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: true fp32-input-denormals: true
fp32-output-denormals: true fp32-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_fneg_f32_denorm ; GFX8-LABEL: name: fcanonicalize_fneg_f32_denorm
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %2:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: fcanonicalize_fneg_f32_denorm ; GFX9-LABEL: name: fcanonicalize_fneg_f32_denorm
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FCANONICALIZE %1 %2:vgpr(s32) = G_FCANONICALIZE %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcanonicalize_fneg_f32_flush name: fcanonicalize_fneg_f32_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: false fp32-input-denormals: false
fp32-output-denormals: false fp32-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_fneg_f32_flush ; GFX8-LABEL: name: fcanonicalize_fneg_f32_flush
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX8: %2:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: fcanonicalize_fneg_f32_flush ; GFX9-LABEL: name: fcanonicalize_fneg_f32_flush
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FCANONICALIZE %1 %2:vgpr(s32) = G_FCANONICALIZE %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcanonicalize_fneg_fabs_f32_denorm name: fcanonicalize_fneg_fabs_f32_denorm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: true fp32-input-denormals: true
fp32-output-denormals: true fp32-output-denormals: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm ; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec ; GFX8: %3:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %3
; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec ; GFX9: %3:vgpr_32 = nofpexcept V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FABS %1 %2:vgpr(s32) = G_FABS %1
%3:vgpr(s32) = G_FCANONICALIZE %2 %3:vgpr(s32) = G_FCANONICALIZE %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fcanonicalize_fneg_fabs_f32_flush name: fcanonicalize_fneg_fabs_f32_flush
legalized: true legalized: true
regBankSelected: true regBankSelected: true
machineFunctionInfo: machineFunctionInfo:
mode: mode:
fp32-input-denormals: false fp32-input-denormals: false
fp32-output-denormals: false fp32-output-denormals: false
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_flush ; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_flush
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec ; GFX8: %3:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec
; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]] ; GFX8: S_ENDPGM 0, implicit %3
; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_flush ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_flush
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec ; GFX9: %3:vgpr_32 = nofpexcept V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]] ; GFX9: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FABS %1 %2:vgpr(s32) = G_FABS %1
%3:vgpr(s32) = G_FCANONICALIZE %2 %3:vgpr(s32) = G_FCANONICALIZE %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: fceil_s32_vv name: fceil_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fceil_s32_vv ; CHECK-LABEL: name: fceil_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_CEIL_F32_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_CEIL_F32_e64_]] ; CHECK: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FCEIL %0 %1:vgpr(s32) = G_FCEIL %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: fceil_s32_vs name: fceil_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: fceil_s32_vs ; CHECK-LABEL: name: fceil_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_CEIL_F32_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_CEIL_F32_e64_]] ; CHECK: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_FCEIL %0 %1:vgpr(s32) = G_FCEIL %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: fceil_s64_sv name: fceil_s64_sv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fceil_s64_sv ; CHECK-LABEL: name: fceil_s64_sv
; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: liveins: $sgpr0_sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[V_CEIL_F64_e64_:%[0-9]+]]:vreg_64 = V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY [[V_CEIL_F64_e64_]] ; CHECK: $vgpr0_vgpr1 = COPY %1
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = G_FCEIL %0 %1:vgpr(s64) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: fceil_s64_vv name: fceil_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fceil_s64_vv ; CHECK-LABEL: name: fceil_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_CEIL_F64_e64_:%[0-9]+]]:vreg_64 = V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY [[V_CEIL_F64_e64_]] ; CHECK: $vgpr0_vgpr1 = COPY %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FCEIL %0 %1:vgpr(s64) = G_FCEIL %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir

Show All 32 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fceil_s16_vv ; GCN-LABEL: name: fceil_s16_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FCEIL %1 %2:vgpr(s16) = G_FCEIL %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: fceil_s16_vs name: fceil_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fceil_s16_vs ; GCN-LABEL: name: fceil_s16_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]] ; GCN: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FCEIL %1 %2:vgpr(s16) = G_FCEIL %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: fceil_fneg_s16_vv name: fceil_fneg_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fceil_fneg_s16_vv ; GCN-LABEL: name: fceil_fneg_s16_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CEIL_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]] ; GCN: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s16) = G_FCEIL %2 %3:vgpr(s16) = G_FCEIL %2
%4:vgpr(s32) = G_ANYEXT %3 %4:vgpr(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

Show All 31 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s32_vv ; WAVE64-LABEL: name: fcmp_oeq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oeq_s32_vv ; WAVE32-LABEL: name: fcmp_oeq_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ogt_s32_vv name: fcmp_ogt_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ogt_s32_vv ; WAVE64-LABEL: name: fcmp_ogt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ogt_s32_vv ; WAVE32-LABEL: name: fcmp_ogt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_oge_s32_vv name: fcmp_oge_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oge_s32_vv ; WAVE64-LABEL: name: fcmp_oge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oge_s32_vv ; WAVE32-LABEL: name: fcmp_oge_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_olt_s32_vv name: fcmp_olt_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_olt_s32_vv ; WAVE64-LABEL: name: fcmp_olt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_olt_s32_vv ; WAVE32-LABEL: name: fcmp_olt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ole_s32_vv name: fcmp_ole_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ole_s32_vv ; WAVE64-LABEL: name: fcmp_ole_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ole_s32_vv ; WAVE32-LABEL: name: fcmp_ole_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_one_s32_vv name: fcmp_one_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_one_s32_vv ; WAVE64-LABEL: name: fcmp_one_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_one_s32_vv ; WAVE32-LABEL: name: fcmp_one_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1 %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ord_s32_vv name: fcmp_ord_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ord_s32_vv ; WAVE64-LABEL: name: fcmp_ord_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ord_s32_vv ; WAVE32-LABEL: name: fcmp_ord_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uno_s32_vv name: fcmp_uno_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uno_s32_vv ; WAVE64-LABEL: name: fcmp_uno_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uno_s32_vv ; WAVE32-LABEL: name: fcmp_uno_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ueq_s32_vv name: fcmp_ueq_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ueq_s32_vv ; WAVE64-LABEL: name: fcmp_ueq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ueq_s32_vv ; WAVE32-LABEL: name: fcmp_ueq_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ugt_s32_vv name: fcmp_ugt_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ugt_s32_vv ; WAVE64-LABEL: name: fcmp_ugt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ugt_s32_vv ; WAVE32-LABEL: name: fcmp_ugt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uge_s32_vv name: fcmp_uge_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uge_s32_vv ; WAVE64-LABEL: name: fcmp_uge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uge_s32_vv ; WAVE32-LABEL: name: fcmp_uge_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ult_s32_vv name: fcmp_ult_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ult_s32_vv ; WAVE64-LABEL: name: fcmp_ult_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ult_s32_vv ; WAVE32-LABEL: name: fcmp_ult_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ule_s32_vv name: fcmp_ule_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ule_s32_vv ; WAVE64-LABEL: name: fcmp_ule_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ule_s32_vv ; WAVE32-LABEL: name: fcmp_ule_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_une_s32_vv name: fcmp_une_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_une_s32_vv ; WAVE64-LABEL: name: fcmp_une_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_une_s32_vv ; WAVE32-LABEL: name: fcmp_une_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1 %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_true_s32_vv name: fcmp_true_s32_vv
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regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oeq_s64_vv ; WAVE64-LABEL: name: fcmp_oeq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oeq_s64_vv ; WAVE32-LABEL: name: fcmp_oeq_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ogt_s64_vv name: fcmp_ogt_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ogt_s64_vv ; WAVE64-LABEL: name: fcmp_ogt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ogt_s64_vv ; WAVE32-LABEL: name: fcmp_ogt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_oge_s64_vv name: fcmp_oge_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oge_s64_vv ; WAVE64-LABEL: name: fcmp_oge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_oge_s64_vv ; WAVE32-LABEL: name: fcmp_oge_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_olt_s64_vv name: fcmp_olt_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_olt_s64_vv ; WAVE64-LABEL: name: fcmp_olt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_olt_s64_vv ; WAVE32-LABEL: name: fcmp_olt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ole_s64_vv name: fcmp_ole_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ole_s64_vv ; WAVE64-LABEL: name: fcmp_ole_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ole_s64_vv ; WAVE32-LABEL: name: fcmp_ole_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_one_s64_vv name: fcmp_one_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_one_s64_vv ; WAVE64-LABEL: name: fcmp_one_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_one_s64_vv ; WAVE32-LABEL: name: fcmp_one_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1 %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ord_s64_vv name: fcmp_ord_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ord_s64_vv ; WAVE64-LABEL: name: fcmp_ord_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ord_s64_vv ; WAVE32-LABEL: name: fcmp_ord_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uno_s64_vv name: fcmp_uno_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uno_s64_vv ; WAVE64-LABEL: name: fcmp_uno_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uno_s64_vv ; WAVE32-LABEL: name: fcmp_uno_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ueq_s64_vv name: fcmp_ueq_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ueq_s64_vv ; WAVE64-LABEL: name: fcmp_ueq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ueq_s64_vv ; WAVE32-LABEL: name: fcmp_ueq_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ugt_s64_vv name: fcmp_ugt_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ugt_s64_vv ; WAVE64-LABEL: name: fcmp_ugt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ugt_s64_vv ; WAVE32-LABEL: name: fcmp_ugt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_uge_s64_vv name: fcmp_uge_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uge_s64_vv ; WAVE64-LABEL: name: fcmp_uge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_uge_s64_vv ; WAVE32-LABEL: name: fcmp_uge_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1 %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ult_s64_vv name: fcmp_ult_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ult_s64_vv ; WAVE64-LABEL: name: fcmp_ult_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ult_s64_vv ; WAVE32-LABEL: name: fcmp_ult_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_ule_s64_vv name: fcmp_ule_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ule_s64_vv ; WAVE64-LABEL: name: fcmp_ule_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_ule_s64_vv ; WAVE32-LABEL: name: fcmp_ule_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1 %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_une_s64_vv name: fcmp_une_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_une_s64_vv ; WAVE64-LABEL: name: fcmp_une_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]] ; WAVE64: S_ENDPGM 0, implicit %2
; WAVE32-LABEL: name: fcmp_une_s64_vv ; WAVE32-LABEL: name: fcmp_une_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]] ; WAVE32: S_ENDPGM 0, implicit %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1 %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fcmp_true_s64_vv name: fcmp_true_s64_vv
Show All 25 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s32_vv_select_user ; WAVE64-LABEL: name: fcmp_oeq_s32_vv_select_user
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], %2, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]] ; WAVE64: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
; WAVE32-LABEL: name: fcmp_oeq_s32_vv_select_user ; WAVE32-LABEL: name: fcmp_oeq_s32_vv_select_user
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], %2, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]] ; WAVE32: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1 %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
%3:vgpr(s32) = G_SELECT %2, %0, %1 %3:vgpr(s32) = G_SELECT %2, %0, %1
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir

Show All 37 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s16_vv ; WAVE64-LABEL: name: fcmp_oeq_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_oeq_s16_vv ; WAVE32-LABEL: name: fcmp_oeq_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3 %4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ogt_s16_vv name: fcmp_ogt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ogt_s16_vv ; WAVE64-LABEL: name: fcmp_ogt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ogt_s16_vv ; WAVE32-LABEL: name: fcmp_ogt_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_oge_s16_vv name: fcmp_oge_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oge_s16_vv ; WAVE64-LABEL: name: fcmp_oge_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_oge_s16_vv ; WAVE32-LABEL: name: fcmp_oge_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(oge), %2, %3 %4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_olt_s16_vv name: fcmp_olt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_olt_s16_vv ; WAVE64-LABEL: name: fcmp_olt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_olt_s16_vv ; WAVE32-LABEL: name: fcmp_olt_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(olt), %2, %3 %4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ole_s16_vv name: fcmp_ole_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ole_s16_vv ; WAVE64-LABEL: name: fcmp_ole_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ole_s16_vv ; WAVE32-LABEL: name: fcmp_ole_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ole), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_one_s16_vv name: fcmp_one_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_one_s16_vv ; WAVE64-LABEL: name: fcmp_one_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_one_s16_vv ; WAVE32-LABEL: name: fcmp_one_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3 %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ord_s16_vv name: fcmp_ord_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ord_s16_vv ; WAVE64-LABEL: name: fcmp_ord_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ord_s16_vv ; WAVE32-LABEL: name: fcmp_ord_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3 %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_uno_s16_vv name: fcmp_uno_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uno_s16_vv ; WAVE64-LABEL: name: fcmp_uno_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_uno_s16_vv ; WAVE32-LABEL: name: fcmp_uno_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(uno), %2, %3 %4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ueq_s16_vv name: fcmp_ueq_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ueq_s16_vv ; WAVE64-LABEL: name: fcmp_ueq_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ueq_s16_vv ; WAVE32-LABEL: name: fcmp_ueq_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ugt_s16_vv name: fcmp_ugt_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ugt_s16_vv ; WAVE64-LABEL: name: fcmp_ugt_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ugt_s16_vv ; WAVE32-LABEL: name: fcmp_ugt_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_uge_s16_vv name: fcmp_uge_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uge_s16_vv ; WAVE64-LABEL: name: fcmp_uge_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_uge_s16_vv ; WAVE32-LABEL: name: fcmp_uge_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(uge), %2, %3 %4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ult_s16_vv name: fcmp_ult_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ult_s16_vv ; WAVE64-LABEL: name: fcmp_ult_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ult_s16_vv ; WAVE32-LABEL: name: fcmp_ult_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ult), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_ule_s16_vv name: fcmp_ule_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ule_s16_vv ; WAVE64-LABEL: name: fcmp_ule_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_ule_s16_vv ; WAVE32-LABEL: name: fcmp_ule_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(ule), %2, %3 %4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fcmp_une_s16_vv name: fcmp_une_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_une_s16_vv ; WAVE64-LABEL: name: fcmp_une_s16_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE64: %4:sreg_64 = nofpexcept V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]] ; WAVE64: S_ENDPGM 0, implicit %4
; WAVE32-LABEL: name: fcmp_une_s16_vv ; WAVE32-LABEL: name: fcmp_une_s16_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec ; WAVE32: %4:sreg_32 = nofpexcept V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]] ; WAVE32: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vcc(s1) = G_FCMP floatpred(une), %2, %3 %4:vcc(s1) = G_FCMP floatpred(une), %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 30 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- ---
name: fexp2_s32_vs name: fexp2_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: fexp2_s32_vs ; CHECK-LABEL: name: fexp2_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_FEXP2 %0 %1:vgpr(s32) = G_FEXP2 %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: fexp2_s32_vv name: fexp2_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: fexp2_s32_vv ; CHECK-LABEL: name: fexp2_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]] ; CHECK: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FEXP2 %0 %1:vgpr(s32) = G_FEXP2 %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir

Show All 32 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; VI-LABEL: name: ffloor_s16_vv ; VI-LABEL: name: ffloor_s16_vv
; VI: liveins: $vgpr0 ; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; VI: %2:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]] ; VI: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FFLOOR %1 %2:vgpr(s16) = G_FFLOOR %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: ffloor_s16_vs name: ffloor_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; VI-LABEL: name: ffloor_s16_vs ; VI-LABEL: name: ffloor_s16_vs
; VI: liveins: $sgpr0 ; VI: liveins: $sgpr0
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; VI: %2:vgpr_32 = nofpexcept V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]] ; VI: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FFLOOR %1 %2:vgpr(s16) = G_FFLOOR %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
Show All 12 Lines bb.0:
; SI: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) ; SI: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]] ; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]] ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16) ; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32) ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: ffloor_fneg_s16_vv ; VI-LABEL: name: ffloor_fneg_s16_vv
; VI: liveins: $vgpr0 ; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; VI: %3:vgpr_32 = nofpexcept V_FLOOR_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]] ; VI: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s16) = G_FFLOOR %2 %3:vgpr(s16) = G_FFLOOR %2
%4:vgpr(s32) = G_ANYEXT %3 %4:vgpr(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: ffloor_s32_vv name: ffloor_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ffloor_s32_vv ; CHECK-LABEL: name: ffloor_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]] ; CHECK: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FFLOOR %0 %1:vgpr(s32) = G_FFLOOR %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: ffloor_s32_vs name: ffloor_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ffloor_s32_vs ; CHECK-LABEL: name: ffloor_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]] ; CHECK: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_FFLOOR %0 %1:vgpr(s32) = G_FFLOOR %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: ffloor_fneg_s32_vs name: ffloor_fneg_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ffloor_fneg_s32_vs ; CHECK-LABEL: name: ffloor_fneg_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]] ; CHECK: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_FNEG %0 %1:sgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FFLOOR %1 %2:vgpr(s32) = G_FFLOOR %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: ffloor_fneg_s32_vv name: ffloor_fneg_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ffloor_fneg_s32_vv ; CHECK-LABEL: name: ffloor_fneg_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vgpr_32 = nofpexcept V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]] ; CHECK: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FFLOOR %1 %2:vgpr(s32) = G_FFLOOR %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: ffloor_s64_vv name: ffloor_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ffloor_s64_vv ; CHECK-LABEL: name: ffloor_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = V_FLOOR_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY [[V_FLOOR_F64_e64_]] ; CHECK: $vgpr0_vgpr1 = COPY %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FFLOOR %0 %1:vgpr(s64) = G_FFLOOR %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
# FIXME: Constant bus restriction # FIXME: Constant bus restriction
# --- # ---
# name: ffloor_s64_vs # name: ffloor_s64_vs
Show All 18 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ffloor_fneg_s64_vv ; CHECK-LABEL: name: ffloor_fneg_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = V_FLOOR_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %2:vreg_64 = nofpexcept V_FLOOR_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY [[V_FLOOR_F64_e64_]] ; CHECK: $vgpr0_vgpr1 = COPY %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FNEG %0 %1:vgpr(s64) = G_FNEG %0
%2:vgpr(s64) = G_FFLOOR %1 %2:vgpr(s64) = G_FFLOOR %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir

Show All 11 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-LABEL: name: fma_f32 ; GFX6-LABEL: name: fma_f32
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %3:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX6: S_ENDPGM 0, implicit %3
; GFX9-DL-LABEL: name: fma_f32 ; GFX9-DL-LABEL: name: fma_f32
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX9-DL: %3:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]] ; GFX9-DL: S_ENDPGM 0, implicit %3
; GFX10-LABEL: name: fma_f32 ; GFX10-LABEL: name: fma_f32
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX10: %3:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]] ; GFX10: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_FMA %0, %1, %2 %3:vgpr(s32) = G_FMA %0, %1, %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fma_f32_fneg_src0 name: fma_f32_fneg_src0
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-LABEL: name: fma_f32_fneg_src0 ; GFX6-LABEL: name: fma_f32_fneg_src0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX6: S_ENDPGM 0, implicit %4
; GFX9-DL-LABEL: name: fma_f32_fneg_src0 ; GFX9-DL-LABEL: name: fma_f32_fneg_src0
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX9-DL: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]] ; GFX9-DL: S_ENDPGM 0, implicit %4
; GFX10-LABEL: name: fma_f32_fneg_src0 ; GFX10-LABEL: name: fma_f32_fneg_src0
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX10: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]] ; GFX10: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_FNEG %0 %3:vgpr(s32) = G_FNEG %0
%4:vgpr(s32) = G_FMA %3, %1, %2 %4:vgpr(s32) = G_FMA %3, %1, %2
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fma_f32_fneg_src1 name: fma_f32_fneg_src1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-LABEL: name: fma_f32_fneg_src1 ; GFX6-LABEL: name: fma_f32_fneg_src1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX6: S_ENDPGM 0, implicit %4
; GFX9-DL-LABEL: name: fma_f32_fneg_src1 ; GFX9-DL-LABEL: name: fma_f32_fneg_src1
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX9-DL: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]] ; GFX9-DL: S_ENDPGM 0, implicit %4
; GFX10-LABEL: name: fma_f32_fneg_src1 ; GFX10-LABEL: name: fma_f32_fneg_src1
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX10: %4:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]] ; GFX10: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_FNEG %1 %3:vgpr(s32) = G_FNEG %1
%4:vgpr(s32) = G_FMA %0, %3, %2 %4:vgpr(s32) = G_FMA %0, %3, %2
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fma_f32_fneg_src2 name: fma_f32_fneg_src2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-LABEL: name: fma_f32_fneg_src2 ; GFX6-LABEL: name: fma_f32_fneg_src2
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX6: S_ENDPGM 0, implicit %4
; GFX9-DL-LABEL: name: fma_f32_fneg_src2 ; GFX9-DL-LABEL: name: fma_f32_fneg_src2
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX9-DL: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX9-DL: S_ENDPGM 0, implicit %4
; GFX10-LABEL: name: fma_f32_fneg_src2 ; GFX10-LABEL: name: fma_f32_fneg_src2
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX10: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX10: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_FNEG %2 %3:vgpr(s32) = G_FNEG %2
%4:vgpr(s32) = G_FMA %0, %1, %3 %4:vgpr(s32) = G_FMA %0, %1, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fma_f32_fabs_src2 name: fma_f32_fabs_src2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-LABEL: name: fma_f32_fabs_src2 ; GFX6-LABEL: name: fma_f32_fabs_src2
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX6: S_ENDPGM 0, implicit %4
; GFX9-DL-LABEL: name: fma_f32_fabs_src2 ; GFX9-DL-LABEL: name: fma_f32_fabs_src2
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX9-DL: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX9-DL: S_ENDPGM 0, implicit %4
; GFX10-LABEL: name: fma_f32_fabs_src2 ; GFX10-LABEL: name: fma_f32_fabs_src2
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX10: %4:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX10: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_FABS %2 %3:vgpr(s32) = G_FABS %2
%4:vgpr(s32) = G_FMA %0, %1, %3 %4:vgpr(s32) = G_FMA %0, %1, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fma_f32_copy_fneg_src2 name: fma_f32_copy_fneg_src2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; GFX6-LABEL: name: fma_f32_copy_fneg_src2 ; GFX6-LABEL: name: fma_f32_copy_fneg_src2
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX6: %5:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX6: S_ENDPGM 0, implicit %5
; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2 ; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2
; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX9-DL: %5:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX9-DL: S_ENDPGM 0, implicit %5
; GFX10-LABEL: name: fma_f32_copy_fneg_src2 ; GFX10-LABEL: name: fma_f32_copy_fneg_src2
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX10: %5:vgpr_32 = nofpexcept V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]] ; GFX10: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_FNEG %2 %3:vgpr(s32) = G_FNEG %2
%4:vgpr(s32) = COPY %3 %4:vgpr(s32) = COPY %3
%5:vgpr(s32) = G_FMA %0, %1, %4 %5:vgpr(s32) = G_FMA %0, %1, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir

Show All 15 Lines bb.0:
; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_on ; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_on
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines bb.0:
; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_off ; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_off
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
Show All 27 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: fmaxnum_ieee_f16_vv name: fmaxnum_ieee_f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fmaxnum_ieee_f16_vv ; CHECK-LABEL: name: fmaxnum_ieee_f16_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %4:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FMAXNUM_IEEE %2, %3 %4:vgpr(s16) = G_FMAXNUM_IEEE %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fmaxnum_ieee_f16_v_fneg_v name: fmaxnum_ieee_f16_v_fneg_v
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fmaxnum_ieee_f16_v_fneg_v ; CHECK-LABEL: name: fmaxnum_ieee_f16_v_fneg_v
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %5:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FNEG %3 %4:vgpr(s16) = G_FNEG %3
%5:vgpr(s16) = G_FMAXNUM_IEEE %2, %4 %5:vgpr(s16) = G_FMAXNUM_IEEE %2, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: fmaxnum_ieee_v2f16_vv name: fmaxnum_ieee_v2f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX9-LABEL: name: fmaxnum_ieee_v2f16_vv ; GFX9-LABEL: name: fmaxnum_ieee_v2f16_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = COPY $vgpr1 %1:vgpr(<2 x s16>) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %0, %1 %2:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir

Show All 16 Lines bb.0:
; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on ; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
Show All 40 Lines bb.0:
; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off ; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
Show All 27 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: fmaxnum_f16_vv name: fmaxnum_f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fmaxnum_f16_vv ; CHECK-LABEL: name: fmaxnum_f16_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %4:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FMAXNUM %2, %3 %4:vgpr(s16) = G_FMAXNUM %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fmaxnum_f16_v_fneg_v name: fmaxnum_f16_v_fneg_v
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fmaxnum_f16_v_fneg_v ; CHECK-LABEL: name: fmaxnum_f16_v_fneg_v
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %5:vgpr_32 = nofpexcept V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FNEG %3 %4:vgpr(s16) = G_FNEG %3
%5:vgpr(s16) = G_FMAXNUM %2, %4 %5:vgpr(s16) = G_FMAXNUM %2, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# FIXME: Ideally this would fail to select with ieee mode enabled. # FIXME: Ideally this would fail to select with ieee mode enabled.
--- ---
name: fmaxnum_v2f16_vv name: fmaxnum_v2f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX9-LABEL: name: fmaxnum_v2f16_vv ; GFX9-LABEL: name: fmaxnum_v2f16_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = COPY $vgpr1 %1:vgpr(<2 x s16>) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_FMAXNUM %0, %1 %2:vgpr(<2 x s16>) = G_FMAXNUM %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir

Show All 15 Lines bb.0:
; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_on ; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_on
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines bb.0:
; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_off ; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_off
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
Show All 27 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: fminnum_ieee_f16_vv name: fminnum_ieee_f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fminnum_ieee_f16_vv ; CHECK-LABEL: name: fminnum_ieee_f16_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %4:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FMINNUM_IEEE %2, %3 %4:vgpr(s16) = G_FMINNUM_IEEE %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fminnum_ieee_f16_v_fneg_v name: fminnum_ieee_f16_v_fneg_v
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fminnum_ieee_f16_v_fneg_v ; CHECK-LABEL: name: fminnum_ieee_f16_v_fneg_v
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %5:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FNEG %3 %4:vgpr(s16) = G_FNEG %3
%5:vgpr(s16) = G_FMINNUM_IEEE %2, %4 %5:vgpr(s16) = G_FMINNUM_IEEE %2, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: fminnum_ieee_v2f16_vv name: fminnum_ieee_v2f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX9-LABEL: name: fminnum_ieee_v2f16_vv ; GFX9-LABEL: name: fminnum_ieee_v2f16_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[V_PK_MIN_F16_:%[0-9]+]]:vgpr_32 = V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MIN_F16_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = COPY $vgpr1 %1:vgpr(<2 x s16>) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_FMINNUM_IEEE %0, %1 %2:vgpr(<2 x s16>) = G_FMINNUM_IEEE %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir

Show All 16 Lines bb.0:
; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
Show All 40 Lines bb.0:
; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off
; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11 ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11 ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13 ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GFX7: %7:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GFX7: %8:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GFX7: %9:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GFX7: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec ; GFX7: %10:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec ; GFX7: %11:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec ; GFX7: %12:vreg_64 = nofpexcept V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec
; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]] ; GFX7: S_ENDPGM 0, implicit %10, implicit %11, implicit %12
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%10:sgpr(s64) = COPY $sgpr10_sgpr11 %10:sgpr(s64) = COPY $sgpr10_sgpr11
%11:vgpr(s64) = COPY $vgpr10_vgpr11 %11:vgpr(s64) = COPY $vgpr10_vgpr11
%12:vgpr(s64) = COPY $vgpr12_vgpr13 %12:vgpr(s64) = COPY $vgpr12_vgpr13
Show All 27 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: fminnum_f16_vv name: fminnum_f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fminnum_f16_vv ; CHECK-LABEL: name: fminnum_f16_vv
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %4:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FMINNUM %2, %3 %4:vgpr(s16) = G_FMINNUM %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: fminnum_f16_v_fneg_v name: fminnum_f16_v_fneg_v
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: fminnum_f16_v_fneg_v ; CHECK-LABEL: name: fminnum_f16_v_fneg_v
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; CHECK: %5:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]] ; CHECK: S_ENDPGM 0, implicit %5
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FNEG %3 %4:vgpr(s16) = G_FNEG %3
%5:vgpr(s16) = G_FMINNUM %2, %4 %5:vgpr(s16) = G_FMINNUM %2, %4
S_ENDPGM 0, implicit %5 S_ENDPGM 0, implicit %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: fminnum_v2f16_vv name: fminnum_v2f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GFX9-LABEL: name: fminnum_v2f16_vv ; GFX9-LABEL: name: fminnum_v2f16_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[V_PK_MIN_F16_:%[0-9]+]]:vgpr_32 = V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MIN_F16_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = COPY $vgpr1 %1:vgpr(<2 x s16>) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_FMINNUM %0, %1 %2:vgpr(<2 x s16>) = G_FMINNUM %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4 liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
; GCN-LABEL: name: fmul_f32 ; GCN-LABEL: name: fmul_f32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %5:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GCN: %6:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY3]], %4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY3]], %5, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY3]], %6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
; fmul vs ; fmul vs
%4:vgpr(s32) = G_FMUL %1, %0 %4:vgpr(s32) = G_FMUL %1, %0
Show All 16 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 liveins: $sgpr0_sgpr1, $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; GCN-LABEL: name: fmul_f64 ; GCN-LABEL: name: fmul_f64
; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; GCN: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %4:vreg_64 = nofpexcept V_MUL_F64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F64_1:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %5:vreg_64 = nofpexcept V_MUL_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F64_2:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec ; GCN: %6:vreg_64 = nofpexcept V_MUL_F64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MUL_F64_]], implicit [[V_MUL_F64_1]], implicit [[V_MUL_F64_2]] ; GCN: S_ENDPGM 0, implicit %4, implicit %5, implicit %6
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr0_vgpr1 %1:vgpr(s64) = COPY $vgpr0_vgpr1
%2:vgpr(s64) = COPY $vgpr2_vgpr3 %2:vgpr(s64) = COPY $vgpr2_vgpr3
%3:vgpr(p1) = COPY $vgpr4_vgpr5 %3:vgpr(p1) = COPY $vgpr4_vgpr5
; fmul vs ; fmul vs
%4:vgpr(s64) = G_FMUL %1, %0 %4:vgpr(s64) = G_FMUL %1, %0
Show All 13 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4 liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
; GCN-LABEL: name: fmul_f16 ; GCN-LABEL: name: fmul_f16
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %7:vgpr_32 = nofpexcept V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %8:vgpr_32 = nofpexcept V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F16_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %9:vgpr_32 = nofpexcept V_MUL_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]], implicit [[V_MUL_F16_e64_1]], implicit [[V_MUL_F16_e64_2]] ; GCN: S_ENDPGM 0, implicit %7, implicit %8, implicit %9
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4 %3:vgpr(p1) = COPY $vgpr3_vgpr4
%4:sgpr(s16) = G_TRUNC %0 %4:sgpr(s16) = G_TRUNC %0
%5:vgpr(s16) = G_TRUNC %1 %5:vgpr(s16) = G_TRUNC %1
%6:vgpr(s16) = G_TRUNC %2 %6:vgpr(s16) = G_TRUNC %2
Show All 17 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3 liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: fmul_modifiers_f32 ; GCN-LABEL: name: fmul_modifiers_f32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 2, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %6:vgpr_32 = nofpexcept V_MUL_F32_e64 2, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %7:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %8:vgpr_32 = nofpexcept V_MUL_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_3:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 1, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %9:vgpr_32 = nofpexcept V_MUL_F32_e64 1, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_4:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %10:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_5:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %11:vgpr_32 = nofpexcept V_MUL_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_6:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %12:vgpr_32 = nofpexcept V_MUL_F32_e64 3, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_7:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %13:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_8:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %14:vgpr_32 = nofpexcept V_MUL_F32_e64 3, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_MUL_F32_e64_9:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %15:vgpr_32 = nofpexcept V_MUL_F32_e64 3, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %6, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %7, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %8, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_3]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_4]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %10, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_5]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_6]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %12, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_7]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_8]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %14, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_9]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY1]], %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(p1) = COPY $vgpr2_vgpr3 %2:vgpr(p1) = COPY $vgpr2_vgpr3
%3:vgpr(s32) = G_FABS %0 %3:vgpr(s32) = G_FABS %0
%4:vgpr(s32) = G_FNEG %0 %4:vgpr(s32) = G_FNEG %0
%5:vgpr(s32) = G_FNEG %3 %5:vgpr(s32) = G_FNEG %3
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
--- ---
name: fmul_v2f16_vv name: fmul_v2f16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX9-LABEL: name: fmul_v2f16_vv ; GFX9-LABEL: name: fmul_v2f16_vv
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %2:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]] ; GFX9: S_ENDPGM 0, implicit %2
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = COPY $vgpr1 %1:vgpr(<2 x s16>) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_FMUL %0, %1 %2:vgpr(<2 x s16>) = G_FMUL %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: fmul_v2f16_fneg_v_fneg_v name: fmul_v2f16_fneg_v_fneg_v
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v ; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %4:vgpr_32 = nofpexcept V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]] ; GFX9: S_ENDPGM 0, implicit %4
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(<2 x s16>) = COPY $vgpr1 %1:vgpr(<2 x s16>) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_FNEG %0 %2:vgpr(<2 x s16>) = G_FNEG %0
%3:vgpr(<2 x s16>) = G_FNEG %1 %3:vgpr(<2 x s16>) = G_FNEG %1
%4:vgpr(<2 x s16>) = G_FMUL %2, %3 %4:vgpr(<2 x s16>) = G_FMUL %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
Show All 9 Lines bb.0:
; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v ; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v
; GFX9: [[COPY:%[0-9]+]]:vgpr_32(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 ; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]] ; GFX9: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
; GFX9: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:vgpr_32(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY2]](s32) ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:vgpr_32(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY2]](s32)
; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_PK_MUL_F16 8, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 8, [[COPY]](<2 x s16>), 0, 0, 0, 0, 0, implicit $mode, implicit $exec ; GFX9: %7:vgpr_32(<2 x s16>) = nofpexcept V_PK_MUL_F16 8, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 8, [[COPY]](<2 x s16>), 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]](<2 x s16>) ; GFX9: S_ENDPGM 0, implicit %7(<2 x s16>)
%0:vgpr(<2 x s16>) = COPY $vgpr0 %0:vgpr(<2 x s16>) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2 %2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_FNEG %3 %4:vgpr(s16) = G_FNEG %3
%5:vgpr(s32) = G_ANYEXT %4 %5:vgpr(s32) = G_ANYEXT %4
%6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2 %6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2
%7:vgpr(<2 x s16>) = G_FMUL %6, %0 %7:vgpr(<2 x s16>) = G_FMUL %6, %0
S_ENDPGM 0, implicit %7 S_ENDPGM 0, implicit %7
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
--- ---
name: fptosi_s32_to_s32_vv name: fptosi_s32_to_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s32_to_s32_vv ; GCN-LABEL: name: fptosi_s32_to_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]] ; GCN: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FPTOSI %0 %1:vgpr(s32) = G_FPTOSI %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: fptosi_s32_to_s32_vs name: fptosi_s32_to_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptosi_s32_to_s32_vs ; GCN-LABEL: name: fptosi_s32_to_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]] ; GCN: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_FPTOSI %0 %1:vgpr(s32) = G_FPTOSI %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: fptosi_s32_to_s32_fneg_vv name: fptosi_s32_to_s32_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv ; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptosi_s16_to_s32_vv name: fptosi_s16_to_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s16_to_s32_vv ; GCN-LABEL: name: fptosi_s16_to_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptosi_s16_to_s32_vs name: fptosi_s16_to_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptosi_s16_to_s32_vs ; GCN-LABEL: name: fptosi_s16_to_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]] ; GCN: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptosi_s16_to_s32_fneg_vv name: fptosi_s16_to_s32_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv ; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]] ; GCN: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s32) = G_FPTOSI %2 %3:vgpr(s32) = G_FPTOSI %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4 liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
; GCN-LABEL: name: fptoui ; GCN-LABEL: name: fptoui
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY2]], %3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY2]], %4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(p1) = COPY $vgpr3_vgpr4 %2:vgpr(p1) = COPY $vgpr3_vgpr4
; fptoui s ; fptoui s
%3:vgpr(s32) = G_FPTOUI %0 %3:vgpr(s32) = G_FPTOUI %0
Show All 13 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptoui_s16_to_s32_vv ; GCN-LABEL: name: fptoui_s16_to_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOUI %1 %2:vgpr(s32) = G_FPTOUI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptoui_s16_to_s32_vs name: fptoui_s16_to_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptoui_s16_to_s32_vs ; GCN-LABEL: name: fptoui_s16_to_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]] ; GCN: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOUI %1 %2:vgpr(s32) = G_FPTOUI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptoui_s16_to_s32_fneg_vv name: fptoui_s16_to_s32_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv ; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]] ; GCN: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s32) = G_FPTOUI %2 %3:vgpr(s32) = G_FPTOUI %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir

Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: frint_s32_vv ; GCN-LABEL: name: frint_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vgpr_32 = nofpexcept V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]] ; GCN: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FRINT %0 %1:vgpr(s32) = G_FRINT %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: frint_s32_vs name: frint_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: frint_s32_vs ; GCN-LABEL: name: frint_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vgpr_32 = nofpexcept V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]] ; GCN: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_FRINT %0 %1:vgpr(s32) = G_FRINT %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: frint_fneg_s32_vv name: frint_fneg_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: frint_fneg_s32_vv ; GCN-LABEL: name: frint_fneg_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_RNDNE_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FRINT %1 %2:vgpr(s32) = G_FRINT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: frint_s64_vv name: frint_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GCN-LABEL: name: frint_s64_vv ; GCN-LABEL: name: frint_s64_vv
; GCN: liveins: $vgpr0_vgpr1 ; GCN: liveins: $vgpr0_vgpr1
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vreg_64 = nofpexcept V_RNDNE_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]] ; GCN: $vgpr0_vgpr1 = COPY %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FRINT %0 %1:vgpr(s64) = G_FRINT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: frint_s64_fneg_vv name: frint_s64_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GCN-LABEL: name: frint_s64_fneg_vv ; GCN-LABEL: name: frint_s64_fneg_vv
; GCN: liveins: $vgpr0_vgpr1 ; GCN: liveins: $vgpr0_vgpr1
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vreg_64 = nofpexcept V_RNDNE_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]] ; GCN: $vgpr0_vgpr1 = COPY %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FNEG %0 %1:vgpr(s64) = G_FNEG %0
%2:vgpr(s64) = G_FRINT %1 %2:vgpr(s64) = G_FRINT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir

Show All 32 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: frint_s16_vv ; GCN-LABEL: name: frint_s16_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FRINT %1 %2:vgpr(s16) = G_FRINT %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: frint_s16_vs name: frint_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: frint_s16_vs ; GCN-LABEL: name: frint_s16_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]] ; GCN: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FRINT %1 %2:vgpr(s16) = G_FRINT %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: frint_fneg_s16_vv name: frint_fneg_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: frint_fneg_s16_vv ; GCN-LABEL: name: frint_fneg_s16_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_RNDNE_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]] ; GCN: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s16) = G_FRINT %2 %3:vgpr(s16) = G_FRINT %2
%4:vgpr(s32) = G_ANYEXT %3 %4:vgpr(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: intrinsic_trunc_s32_vv name: intrinsic_trunc_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: intrinsic_trunc_s32_vv ; CHECK-LABEL: name: intrinsic_trunc_s32_vv
; CHECK: liveins: $vgpr0 ; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_TRUNC_F32_e64_]] ; CHECK: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC_TRUNC %0 %1:vgpr(s32) = G_INTRINSIC_TRUNC %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: intrinsic_trunc_s32_vs name: intrinsic_trunc_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: intrinsic_trunc_s32_vs ; CHECK-LABEL: name: intrinsic_trunc_s32_vs
; CHECK: liveins: $sgpr0 ; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vgpr_32 = nofpexcept V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0 = COPY [[V_TRUNC_F32_e64_]] ; CHECK: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC_TRUNC %0 %1:vgpr(s32) = G_INTRINSIC_TRUNC %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: intrinsic_trunc_s64_sv name: intrinsic_trunc_s64_sv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: intrinsic_trunc_s64_sv ; CHECK-LABEL: name: intrinsic_trunc_s64_sv
; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: liveins: $sgpr0_sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[V_TRUNC_F64_e64_:%[0-9]+]]:vreg_64 = V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY [[V_TRUNC_F64_e64_]] ; CHECK: $vgpr0_vgpr1 = COPY %1
%0:sgpr(s64) = COPY $sgpr0_sgpr1 %0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = G_INTRINSIC_TRUNC %0 %1:vgpr(s64) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: intrinsic_trunc_s64_vv name: intrinsic_trunc_s64_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: intrinsic_trunc_s64_vv ; CHECK-LABEL: name: intrinsic_trunc_s64_vv
; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_TRUNC_F64_e64_:%[0-9]+]]:vreg_64 = V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: %1:vreg_64 = nofpexcept V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY [[V_TRUNC_F64_e64_]] ; CHECK: $vgpr0_vgpr1 = COPY %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_INTRINSIC_TRUNC %0 %1:vgpr(s64) = G_INTRINSIC_TRUNC %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
--- ---
name: intrinsic_trunc_s16_vv name: intrinsic_trunc_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: intrinsic_trunc_s16_vv ; GCN-LABEL: name: intrinsic_trunc_s16_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]] ; GCN: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC_TRUNC %1 %2:vgpr(s16) = G_INTRINSIC_TRUNC %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: intrinsic_trunc_s16_vs name: intrinsic_trunc_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: intrinsic_trunc_s16_vs ; GCN-LABEL: name: intrinsic_trunc_s16_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]] ; GCN: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_INTRINSIC_TRUNC %1 %2:vgpr(s16) = G_INTRINSIC_TRUNC %1
%3:vgpr(s32) = G_ANYEXT %2 %3:vgpr(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: intrinsic_trunc_fneg_s16_vv name: intrinsic_trunc_fneg_s16_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: intrinsic_trunc_fneg_s16_vv ; GCN-LABEL: name: intrinsic_trunc_fneg_s16_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_TRUNC_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]] ; GCN: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s16) = G_INTRINSIC_TRUNC %2 %3:vgpr(s16) = G_INTRINSIC_TRUNC %2
%4:vgpr(s32) = G_ANYEXT %3 %4:vgpr(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; WAVE64-LABEL: name: sitofp_s32_to_s16_vv ; WAVE64-LABEL: name: sitofp_s32_to_s16_vv
; WAVE64: liveins: $vgpr0 ; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec ; WAVE64: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE64: $vgpr0 = COPY %1
; WAVE32-LABEL: name: sitofp_s32_to_s16_vv ; WAVE32-LABEL: name: sitofp_s32_to_s16_vv
; WAVE32: liveins: $vgpr0 ; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec ; WAVE32: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE32: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_SITOFP %0 %1:vgpr(s16) = G_SITOFP %0
%2:vgpr(s32) = G_ANYEXT %1 %2:vgpr(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: sitofp_s32_to_s16_vs name: sitofp_s32_to_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: sitofp_s32_to_s16_vs ; WAVE64-LABEL: name: sitofp_s32_to_s16_vs
; WAVE64: liveins: $sgpr0 ; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec ; WAVE64: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE64: $vgpr0 = COPY %1
; WAVE32-LABEL: name: sitofp_s32_to_s16_vs ; WAVE32-LABEL: name: sitofp_s32_to_s16_vs
; WAVE32: liveins: $sgpr0 ; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec ; WAVE32: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE32: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s16) = G_SITOFP %0 %1:vgpr(s16) = G_SITOFP %0
%2:vgpr(s32) = G_ANYEXT %1 %2:vgpr(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; WAVE64-LABEL: name: uitofp_s32_to_s16_vv ; WAVE64-LABEL: name: uitofp_s32_to_s16_vv
; WAVE64: liveins: $vgpr0 ; WAVE64: liveins: $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec ; WAVE64: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE64: $vgpr0 = COPY %1
; WAVE32-LABEL: name: uitofp_s32_to_s16_vv ; WAVE32-LABEL: name: uitofp_s32_to_s16_vv
; WAVE32: liveins: $vgpr0 ; WAVE32: liveins: $vgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec ; WAVE32: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE32: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_UITOFP %0 %1:vgpr(s16) = G_UITOFP %0
%2:vgpr(s32) = G_ANYEXT %1 %2:vgpr(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: uitofp_s32_to_s16_vs name: uitofp_s32_to_s16_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: uitofp_s32_to_s16_vs ; WAVE64-LABEL: name: uitofp_s32_to_s16_vs
; WAVE64: liveins: $sgpr0 ; WAVE64: liveins: $sgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec ; WAVE64: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec
; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE64: $vgpr0 = COPY %1
; WAVE32-LABEL: name: uitofp_s32_to_s16_vs ; WAVE32-LABEL: name: uitofp_s32_to_s16_vs
; WAVE32: liveins: $sgpr0 ; WAVE32: liveins: $sgpr0
; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec
; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec ; WAVE32: %1:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec
; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]] ; WAVE32: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s16) = G_UITOFP %0 %1:vgpr(s16) = G_UITOFP %0
%2:vgpr(s32) = G_ANYEXT %1 %2:vgpr(s32) = G_ANYEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

llvm/test/CodeGen/X86/GlobalISel/select-add.mir

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
- { id: 2, class: vecr } - { id: 2, class: vecr }
# SSE: %0:vr128 = COPY $xmm0 # SSE: %0:vr128 = COPY $xmm0
# SSE-NEXT: %1:vr128 = COPY $xmm1 # SSE-NEXT: %1:vr128 = COPY $xmm1
# SSE-NEXT: %2:vr128 = ADDPSrr %0, %1 # SSE-NEXT: %2:vr128 = nofpexcept ADDPSrr %0, %1
# AVX: %0:vr128 = COPY $xmm0 # AVX: %0:vr128 = COPY $xmm0
# AVX-NEXT: %1:vr128 = COPY $xmm1 # AVX-NEXT: %1:vr128 = COPY $xmm1
# AVX-NEXT: %2:vr128 = VADDPSrr %0, %1 # AVX-NEXT: %2:vr128 = nofpexcept VADDPSrr %0, %1
# AVX512F: %0:vr128 = COPY $xmm0 # AVX512F: %0:vr128 = COPY $xmm0
# AVX512F-NEXT: 1:vr128 = COPY $xmm1 # AVX512F-NEXT: 1:vr128 = COPY $xmm1
# AVX512F-NEXT: %2:vr128 = VADDPSrr %0, %1 # AVX512F-NEXT: %2:vr128 = nofpexcept VADDPSrr %0, %1
# AVX512VL: %0:vr128x = COPY $xmm0 # AVX512VL: %0:vr128x = COPY $xmm0
# AVX512VL-NEXT: %1:vr128x = COPY $xmm1 # AVX512VL-NEXT: %1:vr128x = COPY $xmm1
# AVX512VL-NEXT: %2:vr128x = VADDPSZ128rr %0, %1 # AVX512VL-NEXT: %2:vr128x = nofpexcept VADDPSZ128rr %0, %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
%0(<4 x s32>) = COPY $xmm0 %0(<4 x s32>) = COPY $xmm0
%1(<4 x s32>) = COPY $xmm1 %1(<4 x s32>) = COPY $xmm1
%2(<4 x s32>) = G_FADD %0, %1 %2(<4 x s32>) = G_FADD %0, %1
$xmm0 = COPY %2(<4 x s32>) $xmm0 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir

Show All 38 Linesbody: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fadd_float ; SSE-LABEL: name: test_fadd_float
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; SSE: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[COPY1]], [[COPY3]] ; SSE: %4:fr32 = nofpexcept ADDSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[ADDSSrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fadd_float ; AVX-LABEL: name: test_fadd_float
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; AVX: [[VADDSSrr:%[0-9]+]]:fr32 = VADDSSrr [[COPY1]], [[COPY3]] ; AVX: %4:fr32 = nofpexcept VADDSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VADDSSrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fadd_float ; AVX512F-LABEL: name: test_fadd_float
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512F: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr32x = nofpexcept VADDSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSSZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fadd_float ; AVX512VL-LABEL: name: test_fadd_float
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512VL: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr32x = nofpexcept VADDSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSSZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128) %0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s32) = G_TRUNC %3(s128) %1:vecr(s32) = G_TRUNC %3(s128)
%4:vecr(s32) = G_FADD %0, %1 %4:vecr(s32) = G_FADD %0, %1
%5:vecr(s128) = G_ANYEXT %4(s32) %5:vecr(s128) = G_ANYEXT %4(s32)
Show All 24 Linesbody: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fadd_double ; SSE-LABEL: name: test_fadd_double
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; SSE: [[ADDSDrr:%[0-9]+]]:fr64 = ADDSDrr [[COPY1]], [[COPY3]] ; SSE: %4:fr64 = nofpexcept ADDSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[ADDSDrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fadd_double ; AVX-LABEL: name: test_fadd_double
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; AVX: [[VADDSDrr:%[0-9]+]]:fr64 = VADDSDrr [[COPY1]], [[COPY3]] ; AVX: %4:fr64 = nofpexcept VADDSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VADDSDrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fadd_double ; AVX512F-LABEL: name: test_fadd_double
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512F: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr64x = nofpexcept VADDSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSDZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fadd_double ; AVX512VL-LABEL: name: test_fadd_double
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512VL: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr64x = nofpexcept VADDSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VADDSDZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128) %0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s64) = G_TRUNC %3(s128) %1:vecr(s64) = G_TRUNC %3(s128)
%4:vecr(s64) = G_FADD %0, %1 %4:vecr(s64) = G_FADD %0, %1
%5:vecr(s128) = G_ANYEXT %4(s64) %5:vecr(s128) = G_ANYEXT %4(s64)
$xmm0 = COPY %5(s128) $xmm0 = COPY %5(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir

Show All 38 Linesbody: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fdiv_float ; SSE-LABEL: name: test_fdiv_float
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; SSE: [[DIVSSrr:%[0-9]+]]:fr32 = DIVSSrr [[COPY1]], [[COPY3]] ; SSE: %4:fr32 = nofpexcept DIVSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSSrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fdiv_float ; AVX-LABEL: name: test_fdiv_float
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; AVX: [[VDIVSSrr:%[0-9]+]]:fr32 = VDIVSSrr [[COPY1]], [[COPY3]] ; AVX: %4:fr32 = nofpexcept VDIVSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VDIVSSrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fdiv_float ; AVX512F-LABEL: name: test_fdiv_float
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512F: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr32x = nofpexcept VDIVSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSSZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fdiv_float ; AVX512VL-LABEL: name: test_fdiv_float
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512VL: [[VDIVSSZrr:%[0-9]+]]:fr32x = VDIVSSZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr32x = nofpexcept VDIVSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSSZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128) %0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s32) = G_TRUNC %3(s128) %1:vecr(s32) = G_TRUNC %3(s128)
%4:vecr(s32) = G_FDIV %0, %1 %4:vecr(s32) = G_FDIV %0, %1
%5:vecr(s128) = G_ANYEXT %4(s32) %5:vecr(s128) = G_ANYEXT %4(s32)
Show All 24 Linesbody: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fdiv_double ; SSE-LABEL: name: test_fdiv_double
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; SSE: [[DIVSDrr:%[0-9]+]]:fr64 = DIVSDrr [[COPY1]], [[COPY3]] ; SSE: %4:fr64 = nofpexcept DIVSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[DIVSDrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fdiv_double ; AVX-LABEL: name: test_fdiv_double
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; AVX: [[VDIVSDrr:%[0-9]+]]:fr64 = VDIVSDrr [[COPY1]], [[COPY3]] ; AVX: %4:fr64 = nofpexcept VDIVSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VDIVSDrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fdiv_double ; AVX512F-LABEL: name: test_fdiv_double
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512F: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr64x = nofpexcept VDIVSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSDZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fdiv_double ; AVX512VL-LABEL: name: test_fdiv_double
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512VL: [[VDIVSDZrr:%[0-9]+]]:fr64x = VDIVSDZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr64x = nofpexcept VDIVSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VDIVSDZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128) %0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s64) = G_TRUNC %3(s128) %1:vecr(s64) = G_TRUNC %3(s128)
%4:vecr(s64) = G_FDIV %0, %1 %4:vecr(s64) = G_FDIV %0, %1
%5:vecr(s128) = G_ANYEXT %4(s64) %5:vecr(s128) = G_ANYEXT %4(s64)
$xmm0 = COPY %5(s128) $xmm0 = COPY %5(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir

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bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fmul_float ; SSE-LABEL: name: test_fmul_float
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; SSE: [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr [[COPY1]], [[COPY3]] ; SSE: %4:fr32 = nofpexcept MULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSSrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fmul_float ; AVX-LABEL: name: test_fmul_float
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; AVX: [[VMULSSrr:%[0-9]+]]:fr32 = VMULSSrr [[COPY1]], [[COPY3]] ; AVX: %4:fr32 = nofpexcept VMULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSSrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fmul_float ; AVX512F-LABEL: name: test_fmul_float
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512F: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fmul_float ; AVX512VL-LABEL: name: test_fmul_float
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512VL: [[VMULSSZrr:%[0-9]+]]:fr32x = VMULSSZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSSZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128) %0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s32) = G_TRUNC %3(s128) %1:vecr(s32) = G_TRUNC %3(s128)
%4:vecr(s32) = G_FMUL %0, %1 %4:vecr(s32) = G_FMUL %0, %1
%5:vecr(s128) = G_ANYEXT %4(s32) %5:vecr(s128) = G_ANYEXT %4(s32)
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bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fmul_double ; SSE-LABEL: name: test_fmul_double
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; SSE: [[MULSDrr:%[0-9]+]]:fr64 = MULSDrr [[COPY1]], [[COPY3]] ; SSE: %4:fr64 = nofpexcept MULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[MULSDrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fmul_double ; AVX-LABEL: name: test_fmul_double
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; AVX: [[VMULSDrr:%[0-9]+]]:fr64 = VMULSDrr [[COPY1]], [[COPY3]] ; AVX: %4:fr64 = nofpexcept VMULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VMULSDrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fmul_double ; AVX512F-LABEL: name: test_fmul_double
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512F: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fmul_double ; AVX512VL-LABEL: name: test_fmul_double
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512VL: [[VMULSDZrr:%[0-9]+]]:fr64x = VMULSDZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VMULSDZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128) %0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s64) = G_TRUNC %3(s128) %1:vecr(s64) = G_TRUNC %3(s128)
%4:vecr(s64) = G_FMUL %0, %1 %4:vecr(s64) = G_FMUL %0, %1
%5:vecr(s128) = G_ANYEXT %4(s64) %5:vecr(s128) = G_ANYEXT %4(s64)
$xmm0 = COPY %5(s128) $xmm0 = COPY %5(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir

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constants: constants:
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; ALL-LABEL: name: test ; ALL-LABEL: name: test
; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; ALL: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; ALL: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY1]] ; ALL: %2:fr64 = nofpexcept CVTSS2SDrr [[COPY1]], implicit $mxcsr
; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY [[CVTSS2SDrr]] ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY %2
; ALL: $xmm0 = COPY [[COPY2]] ; ALL: $xmm0 = COPY [[COPY2]]
; ALL: RET 0, implicit $xmm0 ; ALL: RET 0, implicit $xmm0
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128) %0:vecr(s32) = G_TRUNC %1(s128)
%2:vecr(s64) = G_FPEXT %0(s32) %2:vecr(s64) = G_FPEXT %0(s32)
%3:vecr(s128) = G_ANYEXT %2(s64) %3:vecr(s128) = G_ANYEXT %2(s64)
$xmm0 = COPY %3(s128) $xmm0 = COPY %3(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir

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body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0 liveins: $xmm0
; ALL-LABEL: name: test_fptrunc ; ALL-LABEL: name: test_fptrunc
; ALL: liveins: $xmm0 ; ALL: liveins: $xmm0
; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; ALL: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; ALL: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; ALL: [[CVTSD2SSrr:%[0-9]+]]:fr32 = CVTSD2SSrr [[COPY1]] ; ALL: %2:fr32 = nofpexcept CVTSD2SSrr [[COPY1]], implicit $mxcsr
; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY [[CVTSD2SSrr]] ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY %2
; ALL: $xmm0 = COPY [[COPY2]] ; ALL: $xmm0 = COPY [[COPY2]]
; ALL: RET 0, implicit $xmm0 ; ALL: RET 0, implicit $xmm0
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128) %0:vecr(s64) = G_TRUNC %1(s128)
%2:vecr(s32) = G_FPTRUNC %0(s64) %2:vecr(s32) = G_FPTRUNC %0(s64)
%3:vecr(s128) = G_ANYEXT %2(s32) %3:vecr(s128) = G_ANYEXT %2(s32)
$xmm0 = COPY %3(s128) $xmm0 = COPY %3(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir

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bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fsub_float ; SSE-LABEL: name: test_fsub_float
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; SSE: [[SUBSSrr:%[0-9]+]]:fr32 = SUBSSrr [[COPY1]], [[COPY3]] ; SSE: %4:fr32 = nofpexcept SUBSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSSrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fsub_float ; AVX-LABEL: name: test_fsub_float
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
; AVX: [[VSUBSSrr:%[0-9]+]]:fr32 = VSUBSSrr [[COPY1]], [[COPY3]] ; AVX: %4:fr32 = nofpexcept VSUBSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VSUBSSrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fsub_float ; AVX512F-LABEL: name: test_fsub_float
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512F: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr32x = nofpexcept VSUBSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSSZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fsub_float ; AVX512VL-LABEL: name: test_fsub_float
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
; AVX512VL: [[VSUBSSZrr:%[0-9]+]]:fr32x = VSUBSSZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr32x = nofpexcept VSUBSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSSZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128) %0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s32) = G_TRUNC %3(s128) %1:vecr(s32) = G_TRUNC %3(s128)
%4:vecr(s32) = G_FSUB %0, %1 %4:vecr(s32) = G_FSUB %0, %1
%5:vecr(s128) = G_ANYEXT %4(s32) %5:vecr(s128) = G_ANYEXT %4(s32)
Show All 24 Linesbody: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fsub_double ; SSE-LABEL: name: test_fsub_double
; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; SSE: [[SUBSDrr:%[0-9]+]]:fr64 = SUBSDrr [[COPY1]], [[COPY3]] ; SSE: %4:fr64 = nofpexcept SUBSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY [[SUBSDrr]] ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; SSE: $xmm0 = COPY [[COPY4]] ; SSE: $xmm0 = COPY [[COPY4]]
; SSE: RET 0, implicit $xmm0 ; SSE: RET 0, implicit $xmm0
; AVX-LABEL: name: test_fsub_double ; AVX-LABEL: name: test_fsub_double
; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1 ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]] ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
; AVX: [[VSUBSDrr:%[0-9]+]]:fr64 = VSUBSDrr [[COPY1]], [[COPY3]] ; AVX: %4:fr64 = nofpexcept VSUBSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY [[VSUBSDrr]] ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
; AVX: $xmm0 = COPY [[COPY4]] ; AVX: $xmm0 = COPY [[COPY4]]
; AVX: RET 0, implicit $xmm0 ; AVX: RET 0, implicit $xmm0
; AVX512F-LABEL: name: test_fsub_double ; AVX512F-LABEL: name: test_fsub_double
; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512F: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY1]], [[COPY3]] ; AVX512F: %4:fr64x = nofpexcept VSUBSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSDZrr]] ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512F: $xmm0 = COPY [[COPY4]] ; AVX512F: $xmm0 = COPY [[COPY4]]
; AVX512F: RET 0, implicit $xmm0 ; AVX512F: RET 0, implicit $xmm0
; AVX512VL-LABEL: name: test_fsub_double ; AVX512VL-LABEL: name: test_fsub_double
; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0 ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]] ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1 ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]] ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
; AVX512VL: [[VSUBSDZrr:%[0-9]+]]:fr64x = VSUBSDZrr [[COPY1]], [[COPY3]] ; AVX512VL: %4:fr64x = nofpexcept VSUBSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY [[VSUBSDZrr]] ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
; AVX512VL: $xmm0 = COPY [[COPY4]] ; AVX512VL: $xmm0 = COPY [[COPY4]]
; AVX512VL: RET 0, implicit $xmm0 ; AVX512VL: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0 %2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128) %0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1 %3:vecr(s128) = COPY $xmm1
%1:vecr(s64) = G_TRUNC %3(s128) %1:vecr(s64) = G_TRUNC %3(s128)
%4:vecr(s64) = G_FSUB %0, %1 %4:vecr(s64) = G_FSUB %0, %1
%5:vecr(s128) = G_ANYEXT %4(s64) %5:vecr(s128) = G_ANYEXT %4(s64)
$xmm0 = COPY %5(s128) $xmm0 = COPY %5(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/select-sub.mir

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
- { id: 2, class: vecr } - { id: 2, class: vecr }
# NO_AVX512VL: %0:vr128 = COPY $xmm0 # NO_AVX512VL: %0:vr128 = COPY $xmm0
# NO_AVX512VL: %1:vr128 = COPY $xmm1 # NO_AVX512VL: %1:vr128 = COPY $xmm1
# SSE-NEXT: %2:vr128 = SUBPSrr %0, %1 # SSE-NEXT: %2:vr128 = nofpexcept SUBPSrr %0, %1
# AVX-NEXT: %2:vr128 = VSUBPSrr %0, %1 # AVX-NEXT: %2:vr128 = nofpexcept VSUBPSrr %0, %1
# AVX512F-NEXT: %2:vr128 = VSUBPSrr %0, %1 # AVX512F-NEXT: %2:vr128 = nofpexcept VSUBPSrr %0, %1
# #
# AVX512VL: %0:vr128x = COPY $xmm0 # AVX512VL: %0:vr128x = COPY $xmm0
# AVX512VL: %1:vr128x = COPY $xmm1 # AVX512VL: %1:vr128x = COPY $xmm1
# AVX512VL-NEXT: %2:vr128x = VSUBPSZ128rr %0, %1 # AVX512VL-NEXT: %2:vr128x = nofpexcept VSUBPSZ128rr %0, %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1 liveins: $xmm0, $xmm1
%0(<4 x s32>) = COPY $xmm0 %0(<4 x s32>) = COPY $xmm0
%1(<4 x s32>) = COPY $xmm1 %1(<4 x s32>) = COPY $xmm1
%2(<4 x s32>) = G_FSUB %0, %1 %2(<4 x s32>) = G_FSUB %0, %1
$xmm0 = COPY %2(<4 x s32>) $xmm0 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...

llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: float_to_int8 ; CHECK-LABEL: name: float_to_int8
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]] ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSS2SIrr]].sub_8bit ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit
; CHECK: $al = COPY [[COPY2]] ; CHECK: $al = COPY [[COPY2]]
; CHECK: RET 0, implicit $al ; CHECK: RET 0, implicit $al
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128) %0:vecr(s32) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s32) %3:gpr(s32) = G_FPTOSI %0(s32)
%2:gpr(s8) = G_TRUNC %3(s32) %2:gpr(s8) = G_TRUNC %3(s32)
$al = COPY %2(s8) $al = COPY %2(s8)
RET 0, implicit $al RET 0, implicit $al
Show All 13 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: float_to_int16 ; CHECK-LABEL: name: float_to_int16
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]] ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSS2SIrr]].sub_16bit ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit
; CHECK: $ax = COPY [[COPY2]] ; CHECK: $ax = COPY [[COPY2]]
; CHECK: RET 0, implicit $ax ; CHECK: RET 0, implicit $ax
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128) %0:vecr(s32) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s32) %3:gpr(s32) = G_FPTOSI %0(s32)
%2:gpr(s16) = G_TRUNC %3(s32) %2:gpr(s16) = G_TRUNC %3(s32)
$ax = COPY %2(s16) $ax = COPY %2(s16)
RET 0, implicit $ax RET 0, implicit $ax
Show All 12 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: float_to_int32 ; CHECK-LABEL: name: float_to_int32
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]] ; CHECK: %2:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
; CHECK: $eax = COPY [[CVTTSS2SIrr]] ; CHECK: $eax = COPY %2
; CHECK: RET 0, implicit $eax ; CHECK: RET 0, implicit $eax
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128) %0:vecr(s32) = G_TRUNC %1(s128)
%2:gpr(s32) = G_FPTOSI %0(s32) %2:gpr(s32) = G_FPTOSI %0(s32)
$eax = COPY %2(s32) $eax = COPY %2(s32)
RET 0, implicit $eax RET 0, implicit $eax
... ...
Show All 10 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: float_to_int64 ; CHECK-LABEL: name: float_to_int64
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
; CHECK: [[CVTTSS2SI64rr:%[0-9]+]]:gr64 = CVTTSS2SI64rr [[COPY1]] ; CHECK: %2:gr64 = nofpexcept CVTTSS2SI64rr [[COPY1]], implicit $mxcsr
; CHECK: $rax = COPY [[CVTTSS2SI64rr]] ; CHECK: $rax = COPY %2
; CHECK: RET 0, implicit $rax ; CHECK: RET 0, implicit $rax
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128) %0:vecr(s32) = G_TRUNC %1(s128)
%2:gpr(s64) = G_FPTOSI %0(s32) %2:gpr(s64) = G_FPTOSI %0(s32)
$rax = COPY %2(s64) $rax = COPY %2(s64)
RET 0, implicit $rax RET 0, implicit $rax
... ...
Show All 11 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: double_to_int8 ; CHECK-LABEL: name: double_to_int8
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]] ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSD2SIrr]].sub_8bit ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit
; CHECK: $al = COPY [[COPY2]] ; CHECK: $al = COPY [[COPY2]]
; CHECK: RET 0, implicit $al ; CHECK: RET 0, implicit $al
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128) %0:vecr(s64) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s64) %3:gpr(s32) = G_FPTOSI %0(s64)
%2:gpr(s8) = G_TRUNC %3(s32) %2:gpr(s8) = G_TRUNC %3(s32)
$al = COPY %2(s8) $al = COPY %2(s8)
RET 0, implicit $al RET 0, implicit $al
Show All 13 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: double_to_int16 ; CHECK-LABEL: name: double_to_int16
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]] ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrr]].sub_16bit ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit
; CHECK: $ax = COPY [[COPY2]] ; CHECK: $ax = COPY [[COPY2]]
; CHECK: RET 0, implicit $ax ; CHECK: RET 0, implicit $ax
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128) %0:vecr(s64) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s64) %3:gpr(s32) = G_FPTOSI %0(s64)
%2:gpr(s16) = G_TRUNC %3(s32) %2:gpr(s16) = G_TRUNC %3(s32)
$ax = COPY %2(s16) $ax = COPY %2(s16)
RET 0, implicit $ax RET 0, implicit $ax
Show All 12 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: double_to_int32 ; CHECK-LABEL: name: double_to_int32
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]] ; CHECK: %2:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
; CHECK: $eax = COPY [[CVTTSD2SIrr]] ; CHECK: $eax = COPY %2
; CHECK: RET 0, implicit $eax ; CHECK: RET 0, implicit $eax
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128) %0:vecr(s64) = G_TRUNC %1(s128)
%2:gpr(s32) = G_FPTOSI %0(s64) %2:gpr(s32) = G_FPTOSI %0(s64)
$eax = COPY %2(s32) $eax = COPY %2(s32)
RET 0, implicit $eax RET 0, implicit $eax
... ...
Show All 10 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $xmm0 liveins: $xmm0
; CHECK-LABEL: name: double_to_int64 ; CHECK-LABEL: name: double_to_int64
; CHECK: liveins: $xmm0 ; CHECK: liveins: $xmm0
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY1]] ; CHECK: %2:gr64 = nofpexcept CVTTSD2SI64rr [[COPY1]], implicit $mxcsr
; CHECK: $rax = COPY [[CVTTSD2SI64rr]] ; CHECK: $rax = COPY %2
; CHECK: RET 0, implicit $rax ; CHECK: RET 0, implicit $rax
%1:vecr(s128) = COPY $xmm0 %1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128) %0:vecr(s64) = G_TRUNC %1(s128)
%2:gpr(s64) = G_FPTOSI %0(s64) %2:gpr(s64) = G_FPTOSI %0(s64)
$rax = COPY %2(s64) $rax = COPY %2(s64)
RET 0, implicit $rax RET 0, implicit $rax
... ...

llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesregisters:
- { id: 2, class: vecr } - { id: 2, class: vecr }
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $edi liveins: $edi
; CHECK-LABEL: name: int32_to_float ; CHECK-LABEL: name: int32_to_float
; CHECK: liveins: $edi ; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]] ; CHECK: %1:fr32 = nofpexcept CVTSI2SSrr [[COPY]], implicit $mxcsr
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SSrr]] ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1
; CHECK: $xmm0 = COPY [[COPY1]] ; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0 ; CHECK: RET 0, implicit $xmm0
%0:gpr(s32) = COPY $edi %0:gpr(s32) = COPY $edi
%1:vecr(s32) = G_SITOFP %0(s32) %1:vecr(s32) = G_SITOFP %0(s32)
%2:vecr(s128) = G_ANYEXT %1(s32) %2:vecr(s128) = G_ANYEXT %1(s32)
$xmm0 = COPY %2(s128) $xmm0 = COPY %2(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
Show All 10 Linesregisters:
- { id: 2, class: vecr } - { id: 2, class: vecr }
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $rdi liveins: $rdi
; CHECK-LABEL: name: int64_to_float ; CHECK-LABEL: name: int64_to_float
; CHECK: liveins: $rdi ; CHECK: liveins: $rdi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]] ; CHECK: %1:fr32 = nofpexcept CVTSI642SSrr [[COPY]], implicit $mxcsr
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SSrr]] ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1
; CHECK: $xmm0 = COPY [[COPY1]] ; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0 ; CHECK: RET 0, implicit $xmm0
%0:gpr(s64) = COPY $rdi %0:gpr(s64) = COPY $rdi
%1:vecr(s32) = G_SITOFP %0(s64) %1:vecr(s32) = G_SITOFP %0(s64)
%2:vecr(s128) = G_ANYEXT %1(s32) %2:vecr(s128) = G_ANYEXT %1(s32)
$xmm0 = COPY %2(s128) $xmm0 = COPY %2(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
Show All 38 Linesregisters:
- { id: 2, class: vecr } - { id: 2, class: vecr }
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $rdi liveins: $rdi
; CHECK-LABEL: name: int64_to_double ; CHECK-LABEL: name: int64_to_double
; CHECK: liveins: $rdi ; CHECK: liveins: $rdi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]] ; CHECK: %1:fr64 = nofpexcept CVTSI642SDrr [[COPY]], implicit $mxcsr
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SDrr]] ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1
; CHECK: $xmm0 = COPY [[COPY1]] ; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0 ; CHECK: RET 0, implicit $xmm0
%0:gpr(s64) = COPY $rdi %0:gpr(s64) = COPY $rdi
%1:vecr(s64) = G_SITOFP %0(s64) %1:vecr(s64) = G_SITOFP %0(s64)
%2:vecr(s128) = G_ANYEXT %1(s64) %2:vecr(s128) = G_ANYEXT %1(s64)
$xmm0 = COPY %2(s128) $xmm0 = COPY %2(s128)
RET 0, implicit $xmm0 RET 0, implicit $xmm0
... ...