[AMDGPU][MC] Corrected v_writelane_b32 to fix a decoding bug

[dp]

Summary

v_writelane_b32 is defined so that vdst and vdst_in operand types do not match. This result in incorrect decoding of v_writelane_b32 with dst=v255.

See bug 45193.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/VOP2Instructions.td

 defm V_SUB_I32            : VOP2be_Real_gfx6_gfx7<0x026>;
 defm V_SUBREV_I32         : VOP2be_Real_gfx6_gfx7<0x027>;
 defm V_ADDC_U32           : VOP2be_Real_gfx6_gfx7<0x028>;
 defm V_SUBB_U32           : VOP2be_Real_gfx6_gfx7<0x029>;
 defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
 
 defm V_READLANE_B32 : VOP2Only_Real_gfx6_gfx7<0x001>;
 
-let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
+let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP2Only_Real_gfx6_gfx7<0x002>;
-} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
+} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
 let SubtargetPredicate = isGFX6GFX7 in {
   defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;
 } // End SubtargetPredicate = isGFX6GFX7
 
 defm V_ADD_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x003>;
 defm V_SUB_F32            : VOP2_Real_gfx6_gfx7_gfx10<0x004>;
 defm V_SUBREV_F32         : VOP2_Real_gfx6_gfx7_gfx10<0x005>;

llvm/lib/Target/AMDGPU/VOP3Instructions.td

def _gfx10 :
         VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName);
         let AsmString = asmName # ps.AsmOperands;
       }
   }
 } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
 
 defm V_READLANE_B32  : VOP3_Real_gfx10<0x360>;
 
-let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
+let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
-} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
+} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
 defm V_XOR3_B32           : VOP3_Real_gfx10<0x178>;
 defm V_LSHLREV_B64        : VOP3_Real_gfx10<0x2ff>;
 defm V_LSHRREV_B64        : VOP3_Real_gfx10<0x300>;
 defm V_ASHRREV_I64        : VOP3_Real_gfx10<0x301>;
 defm V_PERM_B32           : VOP3_Real_gfx10<0x344>;
 defm V_XAD_U32            : VOP3_Real_gfx10<0x345>;
 defm V_LSHL_ADD_U32       : VOP3_Real_gfx10<0x346>;

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x05,0x00,0x97,0xd5,0xfe,0x01,0x00,0x00
 
 # GFX10: v_trunc_f64_e64 v[5:6], vcc     ; encoding: [0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00]
 0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00
 
 # GFX10: v_trunc_f64_e64 v[5:6], |v[1:2]| ; encoding: [0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00
 
-# GFX10-FIXME: v_writelane_b32 v255, 0, s2     ; encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
-# 0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
+# GFX10: v_writelane_b32 v255, 0, s2     ; encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
+0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
 
 # GFX10: v_writelane_b32 v5, -1, s2      ; encoding: [0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00]
 0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00
 
 # GFX10: v_writelane_b32 v5, -4.0, s2    ; encoding: [0x05,0x00,0x61,0xd7,0xf7,0x04,0x00,0x00]
 0x05,0x00,0x61,0xd7,0xf7,0x04,0x00,0x00
 
 # GFX10: v_writelane_b32 v5, 0, 0        ; encoding: [0x05,0x00,0x61,0xd7,0x80,0x00,0x01,0x00]