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Differential D80561

AMDGPU/GlobalISel: Select general case for G_PTRMASK
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Authored by arsenm on May 26 2020, 8:19 AM.

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kerbowa
foad
nhaehnle

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arsenm created this revision.May 26 2020, 8:19 AM
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arsenm added a comment.Jun 1 2020, 6:09 AM

ping

arsenm added a comment.Jun 8 2020, 4:53 AM

ping

kerbowa accepted this revision.Jun 14 2020, 12:17 AM

LGTM

This revision is now accepted and ready to land.Jun 14 2020, 12:17 AM
arsenm closed this revision.Jun 14 2020, 10:27 AM

fb51d508eef3f4cd1fee7dc4a0467cb8f4cb116a

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
82 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
381 lines

Diff 266223

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 2,226 Lines • ▼ Show 20 Linesbool AMDGPUInstructionSelector::selectG_FRAME_INDEX_GLOBAL_VALUE(
if (IsVGPR) if (IsVGPR)
I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
return RBI.constrainGenericRegister( return RBI.constrainGenericRegister(
DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI); DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, *MRI);
} }
bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const { bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
Register MaskReg = I.getOperand(2).getReg();
Optional<int64_t> MaskVal = getConstantVRegVal(MaskReg, *MRI);
// TODO: Implement arbitrary cases
if (!MaskVal || !isShiftedMask_64(*MaskVal))
return false;
const uint64_t Mask = *MaskVal;
MachineBasicBlock *BB = I.getParent();
Register DstReg = I.getOperand(0).getReg(); Register DstReg = I.getOperand(0).getReg();
Register SrcReg = I.getOperand(1).getReg(); Register SrcReg = I.getOperand(1).getReg();
Register MaskReg = I.getOperand(2).getReg();
LLT Ty = MRI->getType(DstReg);
LLT MaskTy = MRI->getType(MaskReg);
const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI);
const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID; const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;
if (DstRB != SrcRB) // Should only happen for hand written MIR.
return false;
unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32;
unsigned MovOpc = IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
const TargetRegisterClass &RegRC const TargetRegisterClass &RegRC
= IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass; = IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass;
LLT Ty = MRI->getType(DstReg);
const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB, const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB,
*MRI); *MRI);
const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB, const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB,
*MRI); *MRI);
const TargetRegisterClass *MaskRC =
TRI.getRegClassForTypeOnBank(MaskTy, *MaskRB, *MRI);
if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
!RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI))
return false; return false;
MachineBasicBlock *BB = I.getParent();
const DebugLoc &DL = I.getDebugLoc(); const DebugLoc &DL = I.getDebugLoc();
Register ImmReg = MRI->createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(MovOpc), ImmReg)
.addImm(Mask);
if (Ty.getSizeInBits() == 32) { if (Ty.getSizeInBits() == 32) {
assert(MaskTy.getSizeInBits() == 32 &&
"ptrmask should have been narrowed during legalize");
BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg) BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg)
.addReg(SrcReg) .addReg(SrcReg)
.addReg(ImmReg); .addReg(MaskReg);
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
Register HiReg = MRI->createVirtualRegister(&RegRC); Register HiReg = MRI->createVirtualRegister(&RegRC);
Register LoReg = MRI->createVirtualRegister(&RegRC); Register LoReg = MRI->createVirtualRegister(&RegRC);
Register MaskLo = MRI->createVirtualRegister(&RegRC);
// Extract the subregisters from the source pointer.
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg) BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
.addReg(SrcReg, 0, AMDGPU::sub0); .addReg(SrcReg, 0, AMDGPU::sub0);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg) BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
.addReg(SrcReg, 0, AMDGPU::sub1); .addReg(SrcReg, 0, AMDGPU::sub1);
BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskLo) Register MaskedLo, MaskedHi;
// Try to avoid emitting a bit operation when we only need to touch half of
// the 64-bit pointer.
APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zextOrSelf(64);
const APInt MaskHi32 = APInt::getHighBitsSet(64, 32);
const APInt MaskLo32 = APInt::getLowBitsSet(64, 32);
if ((MaskOnes & MaskLo32) == MaskLo32) {
// If all the bits in the low half are 1, we only need a copy for it.
MaskedLo = LoReg;
} else {
// Extract the mask subregister and apply the and.
Register MaskLo = MRI->createVirtualRegister(&RegRC);
MaskedLo = MRI->createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo)
.addReg(MaskReg, 0, AMDGPU::sub0);
BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedLo)
.addReg(LoReg) .addReg(LoReg)
.addReg(ImmReg); .addReg(MaskLo);
}
if ((MaskOnes & MaskHi32) == MaskHi32) {
// If all the bits in the high half are 1, we only need a copy for it.
MaskedHi = HiReg;
} else {
Register MaskHi = MRI->createVirtualRegister(&RegRC);
MaskedHi = MRI->createVirtualRegister(&RegRC);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskHi)
.addReg(MaskReg, 0, AMDGPU::sub1);
BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedHi)
.addReg(HiReg)
.addReg(MaskHi);
}
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg) BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
.addReg(MaskLo) .addReg(MaskedLo)
.addImm(AMDGPU::sub0) .addImm(AMDGPU::sub0)
.addReg(HiReg) .addReg(MaskedHi)
.addImm(AMDGPU::sub1); .addImm(AMDGPU::sub1);
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
/// Return the register to use for the index value, and the subregister to use /// Return the register to use for the index value, and the subregister to use
/// for the indirectly accessed register. /// for the indirectly accessed register.
static std::pair<Register, unsigned> static std::pair<Register, unsigned>
▲ Show 20 Lines • Show All 1,432 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_sgpr name: ptrmask_p3_s32_sgpr_sgpr_sgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_sgpr ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_sgpr
; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p3) = G_PTRMASK [[COPY]], [[COPY1]](s32) ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3) ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(p3) = G_PTRMASK %0, %1 %2:sgpr(p3) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0 name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xf0f0f0f0
; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: %const:sgpr(s32) = G_CONSTANT i32 -252645136 ; CHECK: %const:sreg_32 = S_MOV_B32 4042322160
; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p3) = G_PTRMASK [[COPY]], %const(s32) ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3) ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -252645136 %const:sgpr(s32) = G_CONSTANT i32 -252645136
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_0xffffffff
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0xffffffff
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: %const:sreg_32 = S_MOV_B32 4294967295
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -1
%1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1
...
---
name: ptrmask_p3_s32_sgpr_sgpr_0x00000000
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_0x00000000
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: %const:sreg_32 = S_MOV_B32 0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 0
%1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1
...
---
name: ptrmask_p3_s32_sgpr_sgpr_clearhi1 name: ptrmask_p3_s32_sgpr_sgpr_clearhi1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi1 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi1
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 ; CHECK: %const:sreg_32 = S_MOV_B32 2147483648
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -2147483648 %const:sgpr(s32) = G_CONSTANT i32 -2147483648
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_clearhi2 name: ptrmask_p3_s32_sgpr_sgpr_clearhi2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi2 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearhi2
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1073741824 ; CHECK: %const:sreg_32 = S_MOV_B32 3221225472
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -1073741824 %const:sgpr(s32) = G_CONSTANT i32 -1073741824
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_clearlo1 name: ptrmask_p3_s32_sgpr_sgpr_clearlo1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo1 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo1
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2 ; CHECK: %const:sreg_32 = S_MOV_B32 4294967294
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -2 %const:sgpr(s32) = G_CONSTANT i32 -2
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_clearlo2 name: ptrmask_p3_s32_sgpr_sgpr_clearlo2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo2 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo2
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 ; CHECK: %const:sreg_32 = S_MOV_B32 4294967292
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -4 %const:sgpr(s32) = G_CONSTANT i32 -4
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_clearlo3 name: ptrmask_p3_s32_sgpr_sgpr_clearlo3
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo3 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo3
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 ; CHECK: %const:sreg_32 = S_MOV_B32 4294967288
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -8 %const:sgpr(s32) = G_CONSTANT i32 -8
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_clearlo4 name: ptrmask_p3_s32_sgpr_sgpr_clearlo4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo4 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo4
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16 ; CHECK: %const:sreg_32 = S_MOV_B32 4294967280
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -16 %const:sgpr(s32) = G_CONSTANT i32 -16
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_s32_sgpr_sgpr_clearlo29 name: ptrmask_p3_s32_sgpr_sgpr_clearlo29
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo29 ; CHECK-LABEL: name: ptrmask_p3_s32_sgpr_sgpr_clearlo29
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -536870912 ; CHECK: %const:sreg_32 = S_MOV_B32 3758096384
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], %const, implicit-def $scc
; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]] ; CHECK: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -536870912 %const:sgpr(s32) = G_CONSTANT i32 -536870912
%1:sgpr(p3) = G_PTRMASK %0, %const %1:sgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_sgpr name: ptrmask_p0_s64_sgpr_sgpr_sgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr
; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 ; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64) ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY3]], [[COPY5]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = COPY $sgpr2_sgpr3 %1:sgpr(s64) = COPY $sgpr2_sgpr3
%2:sgpr(p0) = G_PTRMASK %0, %1 %2:sgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xffffffffffffffff
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_CONSTANT i64 -1
%2:sgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2
...
---
name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0x0000000000000000
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B64_]].sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B64_]].sub1
; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_CONSTANT i64 0
%2:sgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2
...
---
name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0 name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_sgpr_0xf0f0f0f0f0f0f0f0
; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 -1085102592571150096 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4042322160
; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p0) = G_PTRMASK [[COPY]], [[C]](s64) ; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -252645136
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1
; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_CONSTANT i64 -1085102592571150096 %1:sgpr(s64) = G_CONSTANT i64 -1085102592571150096
%2:sgpr(p0) = G_PTRMASK %0, %1 %2:sgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p0_s32_sgpr_sgpr_sgpr name: ptrmask_p0_s32_sgpr_sgpr_sgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
; CHECK-LABEL: name: ptrmask_p0_s32_sgpr_sgpr_sgpr ; CHECK-LABEL: name: ptrmask_p0_s32_sgpr_sgpr_sgpr
; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
; CHECK: [[PTRMASK:%[0-9]+]]:sgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY1]], implicit-def $scc
; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY3]], [[COPY1]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%1:sgpr(s32) = COPY $sgpr2 %1:sgpr(s32) = COPY $sgpr2
%2:sgpr(p0) = G_PTRMASK %0, %1 %2:sgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearhi1 name: ptrmask_p0_s64_sgpr_sgpr_clearhi1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi1 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -9223372036854775808 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648
; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY %const.sub1
; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -9223372036854775808 %const:sgpr(s64) = G_CONSTANT i64 -9223372036854775808
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearhi32 name: ptrmask_p0_s64_sgpr_sgpr_clearhi32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi32 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearhi32
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4294967296 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -4294967296 %const:sgpr(s64) = G_CONSTANT i64 -4294967296
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clear_32 name: ptrmask_p0_s64_sgpr_sgpr_clear_32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clear_32 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clear_32
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967296 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY %const.sub1
; CHECK: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[COPY4]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_AND_B32_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 4294967296 %const:sgpr(s64) = G_CONSTANT i64 4294967296
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearlo1 name: ptrmask_p0_s64_sgpr_sgpr_clearlo1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo1 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2 ; CHECK: %const:sreg_64 = S_MOV_B64 -2
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -2 %const:sgpr(s64) = G_CONSTANT i64 -2
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearlo2 name: ptrmask_p0_s64_sgpr_sgpr_clearlo2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo2 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo2
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 ; CHECK: %const:sreg_64 = S_MOV_B64 -4
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -4 %const:sgpr(s64) = G_CONSTANT i64 -4
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearlo3 name: ptrmask_p0_s64_sgpr_sgpr_clearlo3
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo3 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo3
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 ; CHECK: %const:sreg_64 = S_MOV_B64 -8
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -8 %const:sgpr(s64) = G_CONSTANT i64 -8
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearlo4 name: ptrmask_p0_s64_sgpr_sgpr_clearlo4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo4 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo4
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -16 ; CHECK: %const:sreg_64 = S_MOV_B64 -16
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -16 %const:sgpr(s64) = G_CONSTANT i64 -16
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_sgpr_sgpr_clearlo29 name: ptrmask_p0_s64_sgpr_sgpr_clearlo29
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo29 ; CHECK-LABEL: name: ptrmask_p0_s64_sgpr_sgpr_clearlo29
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -536870912 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3758096384
; CHECK: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; CHECK: %const:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY %const.sub0
; CHECK: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[COPY3]], implicit-def $scc
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s64) = G_CONSTANT i64 -536870912 %const:sgpr(s64) = G_CONSTANT i64 -536870912
%1:sgpr(p0) = G_PTRMASK %0, %const %1:sgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0 name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_0xf0f0f0f0
; CHECK: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: %const:vgpr(s32) = G_CONSTANT i32 -252645136 ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 4042322160, implicit $exec
; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p3) = G_PTRMASK [[COPY]], %const(s32) ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3) ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0 %0:vgpr(p3) = COPY $vgpr0
%const:vgpr(s32) = G_CONSTANT i32 -252645136 %const:vgpr(s32) = G_CONSTANT i32 -252645136
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_vgpr_clearlo1 name: ptrmask_p3_vgpr_vgpr_clearlo1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo1 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo1
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 4294967294, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0 %0:vgpr(p3) = COPY $vgpr0
%const:vgpr(s32) = G_CONSTANT i32 -2 %const:vgpr(s32) = G_CONSTANT i32 -2
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_vgpr_clearlo2 name: ptrmask_p3_vgpr_vgpr_clearlo2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo2 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo2
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0 %0:vgpr(p3) = COPY $vgpr0
%const:vgpr(s32) = G_CONSTANT i32 -4 %const:vgpr(s32) = G_CONSTANT i32 -4
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_vgpr_clearlo3 name: ptrmask_p3_vgpr_vgpr_clearlo3
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo3 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo3
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -8, implicit $exec ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 4294967288, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0 %0:vgpr(p3) = COPY $vgpr0
%const:vgpr(s32) = G_CONSTANT i32 -8 %const:vgpr(s32) = G_CONSTANT i32 -8
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_vgpr_clearlo4 name: ptrmask_p3_vgpr_vgpr_clearlo4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo4 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo4
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 4294967280, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0 %0:vgpr(p3) = COPY $vgpr0
%const:vgpr(s32) = G_CONSTANT i32 -16 %const:vgpr(s32) = G_CONSTANT i32 -16
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_vgpr_clearlo29 name: ptrmask_p3_vgpr_vgpr_clearlo29
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo29 ; CHECK-LABEL: name: ptrmask_p3_vgpr_vgpr_clearlo29
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec ; CHECK: %const:vgpr_32 = V_MOV_B32_e32 3758096384, implicit $exec
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], %const, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] ; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
%0:vgpr(p3) = COPY $vgpr0 %0:vgpr(p3) = COPY $vgpr0
%const:vgpr(s32) = G_CONSTANT i32 -536870912 %const:vgpr(s32) = G_CONSTANT i32 -536870912
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_vgpr_vgpr_vgpr name: ptrmask_p0_s64_vgpr_vgpr_vgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr
; CHECK: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s64) ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
; CHECK: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[COPY5]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3 %1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(p0) = G_PTRMASK %0, %1 %2:vgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0 name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_vgpr_0xf0f0f0f0f0f0f0f0
; CHECK: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 -1085102592571150096 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4042322160, implicit $exec
; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], [[C]](s64) ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -252645136, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1
; CHECK: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY4]], implicit $exec
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_CONSTANT i64 -1085102592571150096 %1:vgpr(s64) = G_CONSTANT i64 -1085102592571150096
%2:vgpr(p0) = G_PTRMASK %0, %1 %2:vgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p0_s32_vgpr_vgpr_vgpr name: ptrmask_p0_s32_vgpr_vgpr_vgpr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2 liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: ptrmask_p0_s32_vgpr_vgpr_vgpr ; CHECK-LABEL: name: ptrmask_p0_s32_vgpr_vgpr_vgpr
; CHECK: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], [[COPY1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0) ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[COPY1]], implicit $exec
; CHECK: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[COPY1]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2 %1:vgpr(s32) = COPY $vgpr2
%2:vgpr(p0) = G_PTRMASK %0, %1 %2:vgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: ptrmask_p0_s32_vgpr_vgpr_vgpr_0xffffffff
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: ptrmask_p0_s32_vgpr_vgpr_vgpr_0xffffffff
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = G_CONSTANT i32 -1
%2:vgpr(p0) = G_PTRMASK %0, %1
S_ENDPGM 0, implicit %2
...
---
name: ptrmask_p0_s64_vgpr_vgpr_clearlo1 name: ptrmask_p0_s64_vgpr_vgpr_clearlo1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo1 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967294, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%const:vgpr(s64) = G_CONSTANT i64 -2 %const:vgpr(s64) = G_CONSTANT i64 -2
%1:vgpr(p0) = G_PTRMASK %0, %const %1:vgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_vgpr_vgpr_clearlo2 name: ptrmask_p0_s64_vgpr_vgpr_clearlo2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo2 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo2
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%const:vgpr(s64) = G_CONSTANT i64 -4 %const:vgpr(s64) = G_CONSTANT i64 -4
%1:vgpr(p0) = G_PTRMASK %0, %const %1:vgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_vgpr_vgpr_clearlo3 name: ptrmask_p0_s64_vgpr_vgpr_clearlo3
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo3 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo3
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967292, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%const:vgpr(s64) = G_CONSTANT i64 -4 %const:vgpr(s64) = G_CONSTANT i64 -4
%1:vgpr(p0) = G_PTRMASK %0, %const %1:vgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_vgpr_vgpr_clearlo4 name: ptrmask_p0_s64_vgpr_vgpr_clearlo4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo4 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo4
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -16, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4294967280, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%const:vgpr(s64) = G_CONSTANT i64 -16 %const:vgpr(s64) = G_CONSTANT i64 -16
%1:vgpr(p0) = G_PTRMASK %0, %const %1:vgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_vgpr_vgpr_clearlo29 name: ptrmask_p0_s64_vgpr_vgpr_clearlo29
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo29 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_vgpr_clearlo29
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -536870912, implicit $exec ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 3758096384, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
; CHECK: %const:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY %const.sub0
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[COPY3]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]] ; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(p0) = COPY $vgpr0_vgpr1 %0:vgpr(p0) = COPY $vgpr0_vgpr1
%const:vgpr(s64) = G_CONSTANT i64 -536870912 %const:vgpr(s64) = G_CONSTANT i64 -536870912
%1:vgpr(p0) = G_PTRMASK %0, %const %1:vgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p3_vgpr_sgpr_clearlo2 name: ptrmask_p3_vgpr_sgpr_clearlo2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; CHECK-LABEL: name: ptrmask_p3_vgpr_sgpr_clearlo2 ; CHECK-LABEL: name: ptrmask_p3_vgpr_sgpr_clearlo2
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec ; CHECK: %const:sgpr(s32) = G_CONSTANT i32 -4
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p3) = G_PTRMASK [[COPY]], %const(s32)
; CHECK: S_ENDPGM 0, implicit [[V_AND_B32_e64_]] ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p3)
%0:sgpr(p3) = COPY $sgpr0 %0:sgpr(p3) = COPY $sgpr0
%const:sgpr(s32) = G_CONSTANT i32 -4 %const:sgpr(s32) = G_CONSTANT i32 -4
%1:vgpr(p3) = G_PTRMASK %0, %const %1:vgpr(p3) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: ptrmask_p0_s64_vgpr_sgpr_clearlo2 name: ptrmask_p0_s64_vgpr_sgpr_clearlo2
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_sgpr_clearlo2 ; CHECK-LABEL: name: ptrmask_p0_s64_vgpr_sgpr_clearlo2
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -4, implicit $exec ; CHECK: %const:sgpr(s32) = G_CONSTANT i32 -4
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0 ; CHECK: [[PTRMASK:%[0-9]+]]:vgpr(p0) = G_PTRMASK [[COPY]], %const(s32)
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1 ; CHECK: S_ENDPGM 0, implicit [[PTRMASK]](p0)
; CHECK: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(p0) = COPY $sgpr0_sgpr1 %0:sgpr(p0) = COPY $sgpr0_sgpr1
%const:sgpr(s32) = G_CONSTANT i32 -4 %const:sgpr(s32) = G_CONSTANT i32 -4
%1:vgpr(p0) = G_PTRMASK %0, %const %1:vgpr(p0) = G_PTRMASK %0, %const
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...