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Differential D80155

[AMDGPU] Fixed selection error for 64 bit extract_subvector
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Authored by rampitec on May 18 2020, 1:29 PM.

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Reviewers
arsenm
msearles
Commits
rG50f3bb13297b: [AMDGPU] Fixed selection error for 64 bit extract_subvector

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Event Timeline

rampitec created this revision.May 18 2020, 1:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 18 2020, 1:29 PM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald Transcript
arsenm accepted this revision.May 18 2020, 1:48 PM
arsenm added inline comments.
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
353

I'm assuming v3f64/v3i64 are still missing

This revision is now accepted and ready to land.May 18 2020, 1:48 PM
rampitec marked an inline comment as done.May 18 2020, 2:10 PM
rampitec added inline comments.
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
353

They don't exist in MVT.

Closed by commit rG50f3bb13297b: [AMDGPU] Fixed selection error for 64 bit extract_subvector (authored by rampitec). · Explain WhyMay 18 2020, 2:39 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
8 lines
test/
CodeGen/
AMDGPU/
172 lines

Diff 264707

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 342 Lines • ▼ Show 20 LinesAMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f64, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f64, Custom);
arsenmUnsubmitted
Not Done
ReplyInline Actions

I'm assuming v3f64/v3i64 are still missing

arsenm: I'm assuming v3f64/v3i64 are still missing
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

They don't exist in MVT.

rampitec: They don't exist in MVT.
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i64, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f64, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i64, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f64, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i64, Custom);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
for (MVT VT : ScalarIntVTs) { for (MVT VT : ScalarIntVTs) {
// These should use [SU]DIVREM, so set them to expand // These should use [SU]DIVREM, so set them to expand
▲ Show 20 Lines • Show All 4,430 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/extract-subvector.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
; CHECK-LABEL: foo ; GCN-LABEL: extract_2xi16
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: buffer_load_ushort ; GCN: buffer_load_ushort
; CHECK: v_bfe_i32 ; GCN: v_bfe_i32
; CHECK: v_bfe_i32 ; GCN: v_bfe_i32
define <2 x i16> @foo(<8 x i16> addrspace(1) * %p0, <8 x i16> addrspace(1) * %p1) { define <2 x i16> @extract_2xi16(<8 x i16> addrspace(1) * %p0, <8 x i16> addrspace(1) * %p1) {
br i1 undef, label %T, label %F br i1 undef, label %T, label %F
T: T:
%t = load volatile <8 x i16>, <8 x i16> addrspace(1) * %p0 %t = load volatile <8 x i16>, <8 x i16> addrspace(1) * %p0
br label %exit br label %exit
F: F:
%f = load volatile <8 x i16>, <8 x i16> addrspace(1) * %p1 %f = load volatile <8 x i16>, <8 x i16> addrspace(1) * %p1
br label %exit br label %exit
exit: exit:
%m = phi <8 x i16> [ %t, %T ], [ %f, %F ] %m = phi <8 x i16> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <8 x i16> %m, <8 x i16> undef, <2 x i32> <i32 0, i32 1> %v2 = shufflevector <8 x i16> %m, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
%b2 = icmp sgt <2 x i16> %v2, <i16 -1, i16 -1> %b2 = icmp sgt <2 x i16> %v2, <i16 -1, i16 -1>
%r2 = select <2 x i1> %b2, <2 x i16> <i16 -32768, i16 -32768>, <2 x i16> <i16 -1, i16 -1> %r2 = select <2 x i1> %b2, <2 x i16> <i16 -32768, i16 -32768>, <2 x i16> <i16 -1, i16 -1>
ret <2 x i16> %r2 ret <2 x i16> %r2
} }
; GCN-LABEL: extract_2xi64
; GCN-COUNT-2: v_cndmask_b32
define <2 x i64> @extract_2xi64(<8 x i64> addrspace(1) * %p0, <8 x i64> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <8 x i64>, <8 x i64> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <8 x i64>, <8 x i64> addrspace(1) * %p1
br label %exit
exit:
%m = phi <8 x i64> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <8 x i64> %m, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
%b2 = icmp sgt <2 x i64> %v2, <i64 -1, i64 -1>
%r2 = select <2 x i1> %b2, <2 x i64> <i64 -32768, i64 -32768>, <2 x i64> <i64 -1, i64 -1>
ret <2 x i64> %r2
}
; GCN-LABEL: extract_4xi64
; GCN-COUNT-4: v_cndmask_b32
define <4 x i64> @extract_4xi64(<8 x i64> addrspace(1) * %p0, <8 x i64> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <8 x i64>, <8 x i64> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <8 x i64>, <8 x i64> addrspace(1) * %p1
br label %exit
exit:
%m = phi <8 x i64> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <8 x i64> %m, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%b2 = icmp sgt <4 x i64> %v2, <i64 -1, i64 -1, i64 -1, i64 -1>
%r2 = select <4 x i1> %b2, <4 x i64> <i64 -32768, i64 -32768, i64 -32768, i64 -32768>, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>
ret <4 x i64> %r2
}
; GCN-LABEL: extract_8xi64
; GCN-COUNT-8: v_cndmask_b32
define <8 x i64> @extract_8xi64(<16 x i64> addrspace(1) * %p0, <16 x i64> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <16 x i64>, <16 x i64> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <16 x i64>, <16 x i64> addrspace(1) * %p1
br label %exit
exit:
%m = phi <16 x i64> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <16 x i64> %m, <16 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%b2 = icmp sgt <8 x i64> %v2, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
%r2 = select <8 x i1> %b2, <8 x i64> <i64 -32768, i64 -32768, i64 -32768, i64 -32768, i64 -32768, i64 -32768, i64 -32768, i64 -32768>, <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
ret <8 x i64> %r2
}
; GCN-LABEL: extract_2xf64
; GCN-COUNT-2: v_cndmask_b32
define <2 x double> @extract_2xf64(<8 x double> addrspace(1) * %p0, <8 x double> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <8 x double>, <8 x double> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <8 x double>, <8 x double> addrspace(1) * %p1
br label %exit
exit:
%m = phi <8 x double> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <8 x double> %m, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%b2 = fcmp ogt <2 x double> %v2, <double -1.0, double -1.0>
%r2 = select <2 x i1> %b2, <2 x double> <double -2.0, double -2.0>, <2 x double> <double -1.0, double -1.0>
ret <2 x double> %r2
}
; GCN-LABEL: extract_4xf64
; GCN-COUNT-4: v_cndmask_b32
define <4 x double> @extract_4xf64(<8 x double> addrspace(1) * %p0, <8 x double> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <8 x double>, <8 x double> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <8 x double>, <8 x double> addrspace(1) * %p1
br label %exit
exit:
%m = phi <8 x double> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <8 x double> %m, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%b2 = fcmp ogt <4 x double> %v2, <double -1.0, double -1.0, double -1.0, double -1.0>
%r2 = select <4 x i1> %b2, <4 x double> <double -2.0, double -2.0, double -2.0, double -2.0>, <4 x double> <double -1.0, double -1.0, double -1.0, double -1.0>
ret <4 x double> %r2
}
; GCN-LABEL: extract_8xf64
; GCN-COUNT-8: v_cndmask_b32
define <8 x double> @extract_8xf64(<16 x double> addrspace(1) * %p0, <16 x double> addrspace(1) * %p1) {
br i1 undef, label %T, label %F
T:
%t = load volatile <16 x double>, <16 x double> addrspace(1) * %p0
br label %exit
F:
%f = load volatile <16 x double>, <16 x double> addrspace(1) * %p1
br label %exit
exit:
%m = phi <16 x double> [ %t, %T ], [ %f, %F ]
%v2 = shufflevector <16 x double> %m, <16 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%b2 = fcmp ogt <8 x double> %v2, <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>
%r2 = select <8 x i1> %b2, <8 x double> <double -2.0, double -2.0, double -2.0, double -2.0, double -2.0, double -2.0, double -2.0, double -2.0>, <8 x double> <double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0, double -1.0>
ret <8 x double> %r2
}