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AMDGPU/GlobalISel: Fix splitting 64-bit extensions
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Authored by arsenm on May 18 2020, 11:19 AM.

Details

Summary

This was replicating the low bits into the high bits, rather than
applying the appropriate extension type.

Diff Detail

Event Timeline

arsenm created this revision.May 18 2020, 11:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 18 2020, 11:19 AM
foad added inline comments.May 20 2020, 1:36 AM
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
2315–2317

Surely the src is always i1 here, so the high part of dst will always be 0 (or undef for anyext)?

arsenm marked 2 inline comments as done.May 20 2020, 5:18 AM
arsenm added inline comments.
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
2315–2317

Not if it’s G_SEXT

foad added inline comments.May 20 2020, 5:44 AM
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
2315–2317

OK, but if it's G_ZEXT the high part is zero and if it's G_SEXT the high part is the same as the low part (and if it's G_ANYEXT the high part is undef). So in no case do you need either a shift or another select.

arsenm updated this revision to Diff 265225.May 20 2020, 6:48 AM
arsenm marked an inline comment as done.

Special case extend from s1 sext case. The zext case emits a constant 0, but I think this depends on whether it's using the CSEMIRbuilder or not. There's not much difference between copy of 0 or second copy of 0

foad accepted this revision.May 20 2020, 7:09 AM
This revision is now accepted and ready to land.May 20 2020, 7:09 AM