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Differential D80005

[x86][NFC] Apply clang-format to X86ISelLowering.h
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Authored by avl on May 15 2020, 6:30 AM.

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Reviewers
aeubanks
craig.topper
rnk
Commits
rGda30c3796aee: [x86][NFC] Apply clang-format to X86ISelLowering.h
Summary
Apply clang-format to X86ISelLowering.h

Diff Detail

Event Timeline

avl created this revision.May 15 2020, 6:30 AM
Herald added subscribers: jfb, hiraditya. · View Herald TranscriptMay 15 2020, 6:30 AM
aeubanks accepted this revision.May 15 2020, 9:01 AM

I've been annoyed at some similar headers not being formatted in the past

This revision is now accepted and ready to land.May 15 2020, 9:01 AM
Harbormaster completed remote builds in B56858: Diff 264226.May 15 2020, 9:12 AM
avl added a comment.May 15 2020, 9:39 AM

Thanks!

Closed by commit rGda30c3796aee: [x86][NFC] Apply clang-format to X86ISelLowering.h (authored by avl). · Explain WhyMay 15 2020, 10:18 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
1467 lines

Diff 264272

llvm/lib/Target/X86/X86ISelLowering.h

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#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetLowering.h"
namespace llvm { namespace llvm {
class X86Subtarget; class X86Subtarget;
class X86TargetMachine; class X86TargetMachine;
namespace X86ISD { namespace X86ISD {
// X86 Specific DAG Nodes // X86 Specific DAG Nodes
enum NodeType : unsigned { enum NodeType : unsigned {
// Start the numbering where the builtin ops leave off. // Start the numbering where the builtin ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END, FIRST_NUMBER = ISD::BUILTIN_OP_END,
/// Bit scan forward. /// Bit scan forward.
BSF, BSF,
/// Bit scan reverse. /// Bit scan reverse.
BSR, BSR,
/// X86 funnel/double shift i16 instructions. These correspond to /// X86 funnel/double shift i16 instructions. These correspond to
/// X86::SHLDW and X86::SHRDW instructions which have different amt /// X86::SHLDW and X86::SHRDW instructions which have different amt
/// modulo rules to generic funnel shifts. /// modulo rules to generic funnel shifts.
/// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD. /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.
FSHL, FSHL,
FSHR, FSHR,
/// Bitwise logical AND of floating point values. This corresponds /// Bitwise logical AND of floating point values. This corresponds
/// to X86::ANDPS or X86::ANDPD. /// to X86::ANDPS or X86::ANDPD.
FAND, FAND,
/// Bitwise logical OR of floating point values. This corresponds /// Bitwise logical OR of floating point values. This corresponds
/// to X86::ORPS or X86::ORPD. /// to X86::ORPS or X86::ORPD.
FOR, FOR,
/// Bitwise logical XOR of floating point values. This corresponds /// Bitwise logical XOR of floating point values. This corresponds
/// to X86::XORPS or X86::XORPD. /// to X86::XORPS or X86::XORPD.
FXOR, FXOR,
/// Bitwise logical ANDNOT of floating point values. This /// Bitwise logical ANDNOT of floating point values. This
/// corresponds to X86::ANDNPS or X86::ANDNPD. /// corresponds to X86::ANDNPS or X86::ANDNPD.
FANDN, FANDN,
/// These operations represent an abstract X86 call /// These operations represent an abstract X86 call
/// instruction, which includes a bunch of information. In particular the /// instruction, which includes a bunch of information. In particular the
/// operands of these node are: /// operands of these node are:
/// ///
/// #0 - The incoming token chain /// #0 - The incoming token chain
/// #1 - The callee /// #1 - The callee
/// #2 - The number of arg bytes the caller pushes on the stack. /// #2 - The number of arg bytes the caller pushes on the stack.
/// #3 - The number of arg bytes the callee pops off the stack. /// #3 - The number of arg bytes the callee pops off the stack.
/// #4 - The value to pass in AL/AX/EAX (optional) /// #4 - The value to pass in AL/AX/EAX (optional)
/// #5 - The value to pass in DL/DX/EDX (optional) /// #5 - The value to pass in DL/DX/EDX (optional)
/// ///
/// The result values of these nodes are: /// The result values of these nodes are:
/// ///
/// #0 - The outgoing token chain /// #0 - The outgoing token chain
/// #1 - The first register result value (optional) /// #1 - The first register result value (optional)
/// #2 - The second register result value (optional) /// #2 - The second register result value (optional)
/// ///
CALL, CALL,
/// Same as call except it adds the NoTrack prefix. /// Same as call except it adds the NoTrack prefix.
NT_CALL, NT_CALL,
/// X86 compare and logical compare instructions. /// X86 compare and logical compare instructions.
CMP, FCMP, COMI, UCOMI, CMP,
FCMP,
COMI,
UCOMI,
/// X86 bit-test instructions. /// X86 bit-test instructions.
BT, BT,
/// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
/// operand, usually produced by a CMP instruction. /// operand, usually produced by a CMP instruction.
SETCC, SETCC,
/// X86 Select /// X86 Select
SELECTS, SELECTS,
// Same as SETCC except it's materialized with a sbb and the value is all // Same as SETCC except it's materialized with a sbb and the value is all
// one's or all zero's. // one's or all zero's.
SETCC_CARRY, // R = carry_bit ? ~0 : 0 SETCC_CARRY, // R = carry_bit ? ~0 : 0
/// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
/// Operands are two FP values to compare; result is a mask of /// Operands are two FP values to compare; result is a mask of
/// 0s or 1s. Generally DTRT for C/C++ with NaNs. /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
FSETCC, FSETCC,
/// X86 FP SETCC, similar to above, but with output as an i1 mask and /// X86 FP SETCC, similar to above, but with output as an i1 mask and
/// and a version with SAE. /// and a version with SAE.
FSETCCM, FSETCCM_SAE, FSETCCM,
FSETCCM_SAE,
/// X86 conditional moves. Operand 0 and operand 1 are the two values /// X86 conditional moves. Operand 0 and operand 1 are the two values
/// to select from. Operand 2 is the condition code, and operand 3 is the /// to select from. Operand 2 is the condition code, and operand 3 is the
/// flag operand produced by a CMP or TEST instruction. /// flag operand produced by a CMP or TEST instruction.
CMOV, CMOV,
/// X86 conditional branches. Operand 0 is the chain operand, operand 1 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
/// is the block to branch if condition is true, operand 2 is the /// is the block to branch if condition is true, operand 2 is the
/// condition code, and operand 3 is the flag operand produced by a CMP /// condition code, and operand 3 is the flag operand produced by a CMP
/// or TEST instruction. /// or TEST instruction.
BRCOND, BRCOND,
/// BRIND node with NoTrack prefix. Operand 0 is the chain operand and /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and
/// operand 1 is the target address. /// operand 1 is the target address.
NT_BRIND, NT_BRIND,
/// Return with a flag operand. Operand 0 is the chain operand, operand /// Return with a flag operand. Operand 0 is the chain operand, operand
/// 1 is the number of bytes of stack to pop. /// 1 is the number of bytes of stack to pop.
RET_FLAG, RET_FLAG,
/// Return from interrupt. Operand 0 is the number of bytes to pop. /// Return from interrupt. Operand 0 is the number of bytes to pop.
IRET, IRET,
/// Repeat fill, corresponds to X86::REP_STOSx. /// Repeat fill, corresponds to X86::REP_STOSx.
REP_STOS, REP_STOS,
/// Repeat move, corresponds to X86::REP_MOVSx. /// Repeat move, corresponds to X86::REP_MOVSx.
REP_MOVS, REP_MOVS,
/// On Darwin, this node represents the result of the popl /// On Darwin, this node represents the result of the popl
/// at function entry, used for PIC code. /// at function entry, used for PIC code.
GlobalBaseReg, GlobalBaseReg,
/// A wrapper node for TargetConstantPool, TargetJumpTable, /// A wrapper node for TargetConstantPool, TargetJumpTable,
/// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
/// MCSymbol and TargetBlockAddress. /// MCSymbol and TargetBlockAddress.
Wrapper, Wrapper,
/// Special wrapper used under X86-64 PIC mode for RIP /// Special wrapper used under X86-64 PIC mode for RIP
/// relative displacements. /// relative displacements.
WrapperRIP, WrapperRIP,
/// Copies a 64-bit value from an MMX vector to the low word /// Copies a 64-bit value from an MMX vector to the low word
/// of an XMM vector, with the high word zero filled. /// of an XMM vector, with the high word zero filled.
MOVQ2DQ, MOVQ2DQ,
/// Copies a 64-bit value from the low word of an XMM vector /// Copies a 64-bit value from the low word of an XMM vector
/// to an MMX vector. /// to an MMX vector.
MOVDQ2Q, MOVDQ2Q,
/// Copies a 32-bit value from the low word of a MMX /// Copies a 32-bit value from the low word of a MMX
/// vector to a GPR. /// vector to a GPR.
MMX_MOVD2W, MMX_MOVD2W,
/// Copies a GPR into the low 32-bit word of a MMX vector /// Copies a GPR into the low 32-bit word of a MMX vector
/// and zero out the high word. /// and zero out the high word.
MMX_MOVW2D, MMX_MOVW2D,
/// Extract an 8-bit value from a vector and zero extend it to /// Extract an 8-bit value from a vector and zero extend it to
/// i32, corresponds to X86::PEXTRB. /// i32, corresponds to X86::PEXTRB.
PEXTRB, PEXTRB,
/// Extract a 16-bit value from a vector and zero extend it to /// Extract a 16-bit value from a vector and zero extend it to
/// i32, corresponds to X86::PEXTRW. /// i32, corresponds to X86::PEXTRW.
PEXTRW, PEXTRW,
/// Insert any element of a 4 x float vector into any element /// Insert any element of a 4 x float vector into any element
/// of a destination 4 x floatvector. /// of a destination 4 x floatvector.
INSERTPS, INSERTPS,
/// Insert the lower 8-bits of a 32-bit value to a vector, /// Insert the lower 8-bits of a 32-bit value to a vector,
/// corresponds to X86::PINSRB. /// corresponds to X86::PINSRB.
PINSRB, PINSRB,
/// Insert the lower 16-bits of a 32-bit value to a vector, /// Insert the lower 16-bits of a 32-bit value to a vector,
/// corresponds to X86::PINSRW. /// corresponds to X86::PINSRW.
PINSRW, PINSRW,
/// Shuffle 16 8-bit values within a vector. /// Shuffle 16 8-bit values within a vector.
PSHUFB, PSHUFB,
/// Compute Sum of Absolute Differences. /// Compute Sum of Absolute Differences.
PSADBW, PSADBW,
/// Compute Double Block Packed Sum-Absolute-Differences /// Compute Double Block Packed Sum-Absolute-Differences
DBPSADBW, DBPSADBW,
/// Bitwise Logical AND NOT of Packed FP values. /// Bitwise Logical AND NOT of Packed FP values.
ANDNP, ANDNP,
/// Blend where the selector is an immediate. /// Blend where the selector is an immediate.
BLENDI, BLENDI,
/// Dynamic (non-constant condition) vector blend where only the sign bits /// Dynamic (non-constant condition) vector blend where only the sign bits
/// of the condition elements are used. This is used to enforce that the /// of the condition elements are used. This is used to enforce that the
/// condition mask is not valid for generic VSELECT optimizations. This /// condition mask is not valid for generic VSELECT optimizations. This
/// is also used to implement the intrinsics. /// is also used to implement the intrinsics.
/// Operands are in VSELECT order: MASK, TRUE, FALSE /// Operands are in VSELECT order: MASK, TRUE, FALSE
BLENDV, BLENDV,
/// Combined add and sub on an FP vector. /// Combined add and sub on an FP vector.
ADDSUB, ADDSUB,
// FP vector ops with rounding mode. // FP vector ops with rounding mode.
FADD_RND, FADDS, FADDS_RND, FADD_RND,
FSUB_RND, FSUBS, FSUBS_RND, FADDS,
FMUL_RND, FMULS, FMULS_RND, FADDS_RND,
FDIV_RND, FDIVS, FDIVS_RND, FSUB_RND,
FMAX_SAE, FMAXS_SAE, FSUBS,
FMIN_SAE, FMINS_SAE, FSUBS_RND,
FSQRT_RND, FSQRTS, FSQRTS_RND, FMUL_RND,
FMULS,
FMULS_RND,
FDIV_RND,
FDIVS,
FDIVS_RND,
FMAX_SAE,
FMAXS_SAE,
FMIN_SAE,
FMINS_SAE,
FSQRT_RND,
FSQRTS,
FSQRTS_RND,
// FP vector get exponent. // FP vector get exponent.
FGETEXP, FGETEXP_SAE, FGETEXPS, FGETEXPS_SAE, FGETEXP,
FGETEXP_SAE,
FGETEXPS,
FGETEXPS_SAE,
// Extract Normalized Mantissas. // Extract Normalized Mantissas.
VGETMANT, VGETMANT_SAE, VGETMANTS, VGETMANTS_SAE, VGETMANT,
VGETMANT_SAE,
VGETMANTS,
VGETMANTS_SAE,
// FP Scale. // FP Scale.
SCALEF, SCALEF_RND, SCALEF,
SCALEFS, SCALEFS_RND, SCALEF_RND,
SCALEFS,
SCALEFS_RND,
// Unsigned Integer average. // Unsigned Integer average.
AVG, AVG,
/// Integer horizontal add/sub. /// Integer horizontal add/sub.
HADD, HADD,
HSUB, HSUB,
/// Floating point horizontal add/sub. /// Floating point horizontal add/sub.
FHADD, FHADD,
FHSUB, FHSUB,
// Detect Conflicts Within a Vector // Detect Conflicts Within a Vector
CONFLICT, CONFLICT,
/// Floating point max and min. /// Floating point max and min.
FMAX, FMIN, FMAX,
FMIN,
/// Commutative FMIN and FMAX. /// Commutative FMIN and FMAX.
FMAXC, FMINC, FMAXC,
FMINC,
/// Scalar intrinsic floating point max and min. /// Scalar intrinsic floating point max and min.
FMAXS, FMINS, FMAXS,
FMINS,
/// Floating point reciprocal-sqrt and reciprocal approximation. /// Floating point reciprocal-sqrt and reciprocal approximation.
/// Note that these typically require refinement /// Note that these typically require refinement
/// in order to obtain suitable precision. /// in order to obtain suitable precision.
FRSQRT, FRCP, FRSQRT,
FRCP,
// AVX-512 reciprocal approximations with a little more precision. // AVX-512 reciprocal approximations with a little more precision.
RSQRT14, RSQRT14S, RCP14, RCP14S, RSQRT14,
RSQRT14S,
RCP14,
RCP14S,
// Thread Local Storage. // Thread Local Storage.
TLSADDR, TLSADDR,
// Thread Local Storage. A call to get the start address // Thread Local Storage. A call to get the start address
// of the TLS block for the current module. // of the TLS block for the current module.
TLSBASEADDR, TLSBASEADDR,
// Thread Local Storage. When calling to an OS provided // Thread Local Storage. When calling to an OS provided
// thunk at the address from an earlier relocation. // thunk at the address from an earlier relocation.
TLSCALL, TLSCALL,
// Exception Handling helpers. // Exception Handling helpers.
EH_RETURN, EH_RETURN,
// SjLj exception handling setjmp. // SjLj exception handling setjmp.
EH_SJLJ_SETJMP, EH_SJLJ_SETJMP,
// SjLj exception handling longjmp. // SjLj exception handling longjmp.
EH_SJLJ_LONGJMP, EH_SJLJ_LONGJMP,
// SjLj exception handling dispatch. // SjLj exception handling dispatch.
EH_SJLJ_SETUP_DISPATCH, EH_SJLJ_SETUP_DISPATCH,
/// Tail call return. See X86TargetLowering::LowerCall for /// Tail call return. See X86TargetLowering::LowerCall for
/// the list of operands. /// the list of operands.
TC_RETURN, TC_RETURN,
// Vector move to low scalar and zero higher vector elements. // Vector move to low scalar and zero higher vector elements.
VZEXT_MOVL, VZEXT_MOVL,
// Vector integer truncate. // Vector integer truncate.
VTRUNC, VTRUNC,
// Vector integer truncate with unsigned/signed saturation. // Vector integer truncate with unsigned/signed saturation.
VTRUNCUS, VTRUNCS, VTRUNCUS,
VTRUNCS,
// Masked version of the above. Used when less than a 128-bit result is // Masked version of the above. Used when less than a 128-bit result is
// produced since the mask only applies to the lower elements and can't // produced since the mask only applies to the lower elements and can't
// be represented by a select. // be represented by a select.
// SRC, PASSTHRU, MASK // SRC, PASSTHRU, MASK
VMTRUNC, VMTRUNCUS, VMTRUNCS, VMTRUNC,
VMTRUNCUS,
VMTRUNCS,
// Vector FP extend. // Vector FP extend.
VFPEXT, VFPEXT_SAE, VFPEXTS, VFPEXTS_SAE, VFPEXT,
VFPEXT_SAE,
VFPEXTS,
VFPEXTS_SAE,
// Vector FP round. // Vector FP round.
VFPROUND, VFPROUND_RND, VFPROUNDS, VFPROUNDS_RND, VFPROUND,
VFPROUND_RND,
VFPROUNDS,
VFPROUNDS_RND,
// Masked version of above. Used for v2f64->v4f32. // Masked version of above. Used for v2f64->v4f32.
// SRC, PASSTHRU, MASK // SRC, PASSTHRU, MASK
VMFPROUND, VMFPROUND,
// 128-bit vector logical left / right shift // 128-bit vector logical left / right shift
VSHLDQ, VSRLDQ, VSHLDQ,
VSRLDQ,
// Vector shift elements // Vector shift elements
VSHL, VSRL, VSRA, VSHL,
VSRL,
VSRA,
// Vector variable shift // Vector variable shift
VSHLV, VSRLV, VSRAV, VSHLV,
VSRLV,
VSRAV,
// Vector shift elements by immediate // Vector shift elements by immediate
VSHLI, VSRLI, VSRAI, VSHLI,
VSRLI,
VSRAI,
// Shifts of mask registers. // Shifts of mask registers.
KSHIFTL, KSHIFTR, KSHIFTL,
KSHIFTR,
// Bit rotate by immediate // Bit rotate by immediate
VROTLI, VROTRI, VROTLI,
VROTRI,
// Vector packed double/float comparison. // Vector packed double/float comparison.
CMPP, CMPP,
// Vector integer comparisons. // Vector integer comparisons.
PCMPEQ, PCMPGT, PCMPEQ,
PCMPGT,
// v8i16 Horizontal minimum and position. // v8i16 Horizontal minimum and position.
PHMINPOS, PHMINPOS,
MULTISHIFT, MULTISHIFT,
/// Vector comparison generating mask bits for fp and /// Vector comparison generating mask bits for fp and
/// integer signed and unsigned data types. /// integer signed and unsigned data types.
CMPM, CMPM,
// Vector comparison with SAE for FP values // Vector comparison with SAE for FP values
CMPM_SAE, CMPM_SAE,
// Arithmetic operations with FLAGS results. // Arithmetic operations with FLAGS results.
ADD, SUB, ADC, SBB, SMUL, UMUL, ADD,
OR, XOR, AND, SUB,
ADC,
SBB,
SMUL,
UMUL,
OR,
XOR,
AND,
// Bit field extract. // Bit field extract.
BEXTR, BEXTR,
// Zero High Bits Starting with Specified Bit Position. // Zero High Bits Starting with Specified Bit Position.
BZHI, BZHI,
// Parallel extract and deposit. // Parallel extract and deposit.
PDEP, PEXT, PDEP,
PEXT,
// X86-specific multiply by immediate. // X86-specific multiply by immediate.
MUL_IMM, MUL_IMM,
// Vector sign bit extraction. // Vector sign bit extraction.
MOVMSK, MOVMSK,
// Vector bitwise comparisons. // Vector bitwise comparisons.
PTEST, PTEST,
// Vector packed fp sign bitwise comparisons. // Vector packed fp sign bitwise comparisons.
TESTP, TESTP,
// OR/AND test for masks. // OR/AND test for masks.
KORTEST, KORTEST,
KTEST, KTEST,
// ADD for masks. // ADD for masks.
KADD, KADD,
// Several flavors of instructions with vector shuffle behaviors. // Several flavors of instructions with vector shuffle behaviors.
// Saturated signed/unnsigned packing. // Saturated signed/unnsigned packing.
PACKSS, PACKSS,
PACKUS, PACKUS,
// Intra-lane alignr. // Intra-lane alignr.
PALIGNR, PALIGNR,
// AVX512 inter-lane alignr. // AVX512 inter-lane alignr.
VALIGN, VALIGN,
PSHUFD, PSHUFD,
PSHUFHW, PSHUFHW,
PSHUFLW, PSHUFLW,
SHUFP, SHUFP,
// VBMI2 Concat & Shift. // VBMI2 Concat & Shift.
VSHLD, VSHLD,
VSHRD, VSHRD,
VSHLDV, VSHLDV,
VSHRDV, VSHRDV,
//Shuffle Packed Values at 128-bit granularity. // Shuffle Packed Values at 128-bit granularity.
SHUF128, SHUF128,
MOVDDUP, MOVDDUP,
MOVSHDUP, MOVSHDUP,
MOVSLDUP, MOVSLDUP,
MOVLHPS, MOVLHPS,
MOVHLPS, MOVHLPS,
MOVSD, MOVSD,
MOVSS, MOVSS,
UNPCKL, UNPCKL,
UNPCKH, UNPCKH,
VPERMILPV, VPERMILPV,
VPERMILPI, VPERMILPI,
VPERMI, VPERMI,
VPERM2X128, VPERM2X128,
// Variable Permute (VPERM). // Variable Permute (VPERM).
// Res = VPERMV MaskV, V0 // Res = VPERMV MaskV, V0
VPERMV, VPERMV,
// 3-op Variable Permute (VPERMT2). // 3-op Variable Permute (VPERMT2).
// Res = VPERMV3 V0, MaskV, V1 // Res = VPERMV3 V0, MaskV, V1
VPERMV3, VPERMV3,
// Bitwise ternary logic. // Bitwise ternary logic.
VPTERNLOG, VPTERNLOG,
// Fix Up Special Packed Float32/64 values. // Fix Up Special Packed Float32/64 values.
VFIXUPIMM, VFIXUPIMM_SAE, VFIXUPIMM,
VFIXUPIMMS, VFIXUPIMMS_SAE, VFIXUPIMM_SAE,
VFIXUPIMMS,
VFIXUPIMMS_SAE,
// Range Restriction Calculation For Packed Pairs of Float32/64 values. // Range Restriction Calculation For Packed Pairs of Float32/64 values.
VRANGE, VRANGE_SAE, VRANGES, VRANGES_SAE, VRANGE,
VRANGE_SAE,
VRANGES,
VRANGES_SAE,
// Reduce - Perform Reduction Transformation on scalar\packed FP. // Reduce - Perform Reduction Transformation on scalar\packed FP.
VREDUCE, VREDUCE_SAE, VREDUCES, VREDUCES_SAE, VREDUCE,
VREDUCE_SAE,
VREDUCES,
VREDUCES_SAE,
// RndScale - Round FP Values To Include A Given Number Of Fraction Bits. // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
// Also used by the legacy (V)ROUND intrinsics where we mask out the // Also used by the legacy (V)ROUND intrinsics where we mask out the
// scaling part of the immediate. // scaling part of the immediate.
VRNDSCALE, VRNDSCALE_SAE, VRNDSCALES, VRNDSCALES_SAE, VRNDSCALE,
VRNDSCALE_SAE,
VRNDSCALES,
VRNDSCALES_SAE,
// Tests Types Of a FP Values for packed types. // Tests Types Of a FP Values for packed types.
VFPCLASS, VFPCLASS,
// Tests Types Of a FP Values for scalar types. // Tests Types Of a FP Values for scalar types.
VFPCLASSS, VFPCLASSS,
// Broadcast (splat) scalar or element 0 of a vector. If the operand is // Broadcast (splat) scalar or element 0 of a vector. If the operand is
// a vector, this node may change the vector length as part of the splat. // a vector, this node may change the vector length as part of the splat.
VBROADCAST, VBROADCAST,
// Broadcast mask to vector. // Broadcast mask to vector.
VBROADCASTM, VBROADCASTM,
// Broadcast subvector to vector. // Broadcast subvector to vector.
SUBV_BROADCAST, SUBV_BROADCAST,
/// SSE4A Extraction and Insertion. /// SSE4A Extraction and Insertion.
EXTRQI, INSERTQI, EXTRQI,
INSERTQI,
// XOP arithmetic/logical shifts. // XOP arithmetic/logical shifts.
VPSHA, VPSHL, VPSHA,
VPSHL,
// XOP signed/unsigned integer comparisons. // XOP signed/unsigned integer comparisons.
VPCOM, VPCOMU, VPCOM,
VPCOMU,
// XOP packed permute bytes. // XOP packed permute bytes.
VPPERM, VPPERM,
// XOP two source permutation. // XOP two source permutation.
VPERMIL2, VPERMIL2,
// Vector multiply packed unsigned doubleword integers. // Vector multiply packed unsigned doubleword integers.
PMULUDQ, PMULUDQ,
// Vector multiply packed signed doubleword integers. // Vector multiply packed signed doubleword integers.
PMULDQ, PMULDQ,
// Vector Multiply Packed UnsignedIntegers with Round and Scale. // Vector Multiply Packed UnsignedIntegers with Round and Scale.
MULHRS, MULHRS,
// Multiply and Add Packed Integers. // Multiply and Add Packed Integers.
VPMADDUBSW, VPMADDWD, VPMADDUBSW,
VPMADDWD,
// AVX512IFMA multiply and add. // AVX512IFMA multiply and add.
// NOTE: These are different than the instruction and perform // NOTE: These are different than the instruction and perform
// op0 x op1 + op2. // op0 x op1 + op2.
VPMADD52L, VPMADD52H, VPMADD52L,
VPMADD52H,
// VNNI // VNNI
VPDPBUSD, VPDPBUSD,
VPDPBUSDS, VPDPBUSDS,
VPDPWSSD, VPDPWSSD,
VPDPWSSDS, VPDPWSSDS,
// FMA nodes. // FMA nodes.
// We use the target independent ISD::FMA for the non-inverted case. // We use the target independent ISD::FMA for the non-inverted case.
FNMADD, FNMADD,
FMSUB, FMSUB,
FNMSUB, FNMSUB,
FMADDSUB, FMADDSUB,
FMSUBADD, FMSUBADD,
// FMA with rounding mode. // FMA with rounding mode.
FMADD_RND, FMADD_RND,
FNMADD_RND, FNMADD_RND,
FMSUB_RND, FMSUB_RND,
FNMSUB_RND, FNMSUB_RND,
FMADDSUB_RND, FMADDSUB_RND,
FMSUBADD_RND, FMSUBADD_RND,
// Compress and expand. // Compress and expand.
COMPRESS, COMPRESS,
EXPAND, EXPAND,
// Bits shuffle // Bits shuffle
VPSHUFBITQMB, VPSHUFBITQMB,
// Convert Unsigned/Integer to Floating-Point Value with rounding mode. // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
SINT_TO_FP_RND, UINT_TO_FP_RND, SINT_TO_FP_RND,
SCALAR_SINT_TO_FP, SCALAR_UINT_TO_FP, UINT_TO_FP_RND,
SCALAR_SINT_TO_FP_RND, SCALAR_UINT_TO_FP_RND, SCALAR_SINT_TO_FP,
SCALAR_UINT_TO_FP,
SCALAR_SINT_TO_FP_RND,
SCALAR_UINT_TO_FP_RND,
// Vector float/double to signed/unsigned integer. // Vector float/double to signed/unsigned integer.
CVTP2SI, CVTP2UI, CVTP2SI_RND, CVTP2UI_RND, CVTP2SI,
CVTP2UI,
CVTP2SI_RND,
CVTP2UI_RND,
// Scalar float/double to signed/unsigned integer. // Scalar float/double to signed/unsigned integer.
CVTS2SI, CVTS2UI, CVTS2SI_RND, CVTS2UI_RND, CVTS2SI,
CVTS2UI,
CVTS2SI_RND,
CVTS2UI_RND,
// Vector float/double to signed/unsigned integer with truncation. // Vector float/double to signed/unsigned integer with truncation.
CVTTP2SI, CVTTP2UI, CVTTP2SI_SAE, CVTTP2UI_SAE, CVTTP2SI,
CVTTP2UI,
CVTTP2SI_SAE,
CVTTP2UI_SAE,
// Scalar float/double to signed/unsigned integer with truncation. // Scalar float/double to signed/unsigned integer with truncation.
CVTTS2SI, CVTTS2UI, CVTTS2SI_SAE, CVTTS2UI_SAE, CVTTS2SI,
CVTTS2UI,
CVTTS2SI_SAE,
CVTTS2UI_SAE,
// Vector signed/unsigned integer to float/double. // Vector signed/unsigned integer to float/double.
CVTSI2P, CVTUI2P, CVTSI2P,
CVTUI2P,
// Masked versions of above. Used for v2f64->v4f32. // Masked versions of above. Used for v2f64->v4f32.
// SRC, PASSTHRU, MASK // SRC, PASSTHRU, MASK
MCVTP2SI, MCVTP2UI, MCVTTP2SI, MCVTTP2UI, MCVTP2SI,
MCVTSI2P, MCVTUI2P, MCVTP2UI,
MCVTTP2SI,
MCVTTP2UI,
MCVTSI2P,
MCVTUI2P,
// Vector float to bfloat16. // Vector float to bfloat16.
// Convert TWO packed single data to one packed BF16 data // Convert TWO packed single data to one packed BF16 data
CVTNE2PS2BF16, CVTNE2PS2BF16,
// Convert packed single data to packed BF16 data // Convert packed single data to packed BF16 data
CVTNEPS2BF16, CVTNEPS2BF16,
// Masked version of above. // Masked version of above.
// SRC, PASSTHRU, MASK // SRC, PASSTHRU, MASK
MCVTNEPS2BF16, MCVTNEPS2BF16,
// Dot product of BF16 pairs to accumulated into // Dot product of BF16 pairs to accumulated into
// packed single precision. // packed single precision.
DPBF16PS, DPBF16PS,
// Save xmm argument registers to the stack, according to %al. An operator // Save xmm argument registers to the stack, according to %al. An operator
// is needed so that this can be expanded with control flow. // is needed so that this can be expanded with control flow.
VASTART_SAVE_XMM_REGS, VASTART_SAVE_XMM_REGS,
// Windows's _chkstk call to do stack probing. // Windows's _chkstk call to do stack probing.
WIN_ALLOCA, WIN_ALLOCA,
// For allocating variable amounts of stack space when using // For allocating variable amounts of stack space when using
// segmented stacks. Check if the current stacklet has enough space, and // segmented stacks. Check if the current stacklet has enough space, and
// falls back to heap allocation if not. // falls back to heap allocation if not.
SEG_ALLOCA, SEG_ALLOCA,
// For allocating stack space when using stack clash protector. // For allocating stack space when using stack clash protector.
// Allocation is performed by block, and each block is probed. // Allocation is performed by block, and each block is probed.
PROBED_ALLOCA, PROBED_ALLOCA,
// Memory barriers. // Memory barriers.
MEMBARRIER, MEMBARRIER,
MFENCE, MFENCE,
// Get a random integer and indicate whether it is valid in CF. // Get a random integer and indicate whether it is valid in CF.
RDRAND, RDRAND,
// Get a NIST SP800-90B & C compliant random integer and // Get a NIST SP800-90B & C compliant random integer and
// indicate whether it is valid in CF. // indicate whether it is valid in CF.
RDSEED, RDSEED,
// Protection keys // Protection keys
// RDPKRU - Operand 0 is chain. Operand 1 is value for ECX. // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX.
// WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is
// value for ECX. // value for ECX.
RDPKRU, WRPKRU, RDPKRU,
WRPKRU,
// SSE42 string comparisons. // SSE42 string comparisons.
// These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG
// will emit one or two instructions based on which results are used. If // will emit one or two instructions based on which results are used. If
// flags and index/mask this allows us to use a single instruction since // flags and index/mask this allows us to use a single instruction since
// we won't have to pick and opcode for flags. Instead we can rely on the // we won't have to pick and opcode for flags. Instead we can rely on the
// DAG to CSE everything and decide at isel. // DAG to CSE everything and decide at isel.
PCMPISTR, PCMPISTR,
PCMPESTR, PCMPESTR,
// Test if in transactional execution. // Test if in transactional execution.
XTEST, XTEST,
// ERI instructions. // ERI instructions.
RSQRT28, RSQRT28_SAE, RSQRT28S, RSQRT28S_SAE, RSQRT28,
RCP28, RCP28_SAE, RCP28S, RCP28S_SAE, EXP2, EXP2_SAE, RSQRT28_SAE,
RSQRT28S,
RSQRT28S_SAE,
RCP28,
RCP28_SAE,
RCP28S,
RCP28S_SAE,
EXP2,
EXP2_SAE,
// Conversions between float and half-float. // Conversions between float and half-float.
CVTPS2PH, CVTPH2PS, CVTPH2PS_SAE, CVTPS2PH,
CVTPH2PS,
CVTPH2PS_SAE,
// Masked version of above. // Masked version of above.
// SRC, RND, PASSTHRU, MASK // SRC, RND, PASSTHRU, MASK
MCVTPS2PH, MCVTPS2PH,
// Galois Field Arithmetic Instructions // Galois Field Arithmetic Instructions
GF2P8AFFINEINVQB, GF2P8AFFINEQB, GF2P8MULB, GF2P8AFFINEINVQB,
GF2P8AFFINEQB,
GF2P8MULB,
// LWP insert record. // LWP insert record.
LWPINS, LWPINS,
// User level wait // User level wait
UMWAIT, TPAUSE, UMWAIT,
TPAUSE,
// Enqueue Stores Instructions // Enqueue Stores Instructions
ENQCMD, ENQCMDS, ENQCMD,
ENQCMDS,
// For avx512-vp2intersect // For avx512-vp2intersect
VP2INTERSECT, VP2INTERSECT,
/// X86 strict FP compare instructions. /// X86 strict FP compare instructions.
STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
STRICT_FCMPS, STRICT_FCMPS,
// Vector packed double/float comparison. // Vector packed double/float comparison.
STRICT_CMPP, STRICT_CMPP,
/// Vector comparison generating mask bits for fp and /// Vector comparison generating mask bits for fp and
/// integer signed and unsigned data types. /// integer signed and unsigned data types.
STRICT_CMPM, STRICT_CMPM,
// Vector float/double to signed/unsigned integer with truncation. // Vector float/double to signed/unsigned integer with truncation.
STRICT_CVTTP2SI, STRICT_CVTTP2UI, STRICT_CVTTP2SI,
STRICT_CVTTP2UI,
// Vector FP extend. // Vector FP extend.
STRICT_VFPEXT, STRICT_VFPEXT,
// Vector FP round. // Vector FP round.
STRICT_VFPROUND, STRICT_VFPROUND,
// RndScale - Round FP Values To Include A Given Number Of Fraction Bits. // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
// Also used by the legacy (V)ROUND intrinsics where we mask out the // Also used by the legacy (V)ROUND intrinsics where we mask out the
// scaling part of the immediate. // scaling part of the immediate.
STRICT_VRNDSCALE, STRICT_VRNDSCALE,
// Vector signed/unsigned integer to float/double. // Vector signed/unsigned integer to float/double.
STRICT_CVTSI2P, STRICT_CVTUI2P, STRICT_CVTSI2P,
STRICT_CVTUI2P,
// Strict FMA nodes. // Strict FMA nodes.
STRICT_FNMADD, STRICT_FMSUB, STRICT_FNMSUB, STRICT_FNMADD,
STRICT_FMSUB,
STRICT_FNMSUB,
// Conversions between float and half-float. // Conversions between float and half-float.
STRICT_CVTPS2PH, STRICT_CVTPH2PS, STRICT_CVTPS2PH,
STRICT_CVTPH2PS,
// Compare and swap. // Compare and swap.
LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
LCMPXCHG8_DAG, LCMPXCHG8_DAG,
LCMPXCHG16_DAG, LCMPXCHG16_DAG,
LCMPXCHG8_SAVE_EBX_DAG, LCMPXCHG8_SAVE_EBX_DAG,
LCMPXCHG16_SAVE_RBX_DAG, LCMPXCHG16_SAVE_RBX_DAG,
/// LOCK-prefixed arithmetic read-modify-write instructions. /// LOCK-prefixed arithmetic read-modify-write instructions.
/// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS) /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
LADD, LSUB, LOR, LXOR, LAND, LADD,
LSUB,
LOR,
LXOR,
LAND,
// Load, scalar_to_vector, and zero extend. // Load, scalar_to_vector, and zero extend.
VZEXT_LOAD, VZEXT_LOAD,
// extract_vector_elt, store. // extract_vector_elt, store.
VEXTRACT_STORE, VEXTRACT_STORE,
// scalar broadcast from memory // scalar broadcast from memory
VBROADCAST_LOAD, VBROADCAST_LOAD,
// Store FP control world into i16 memory. // Store FP control world into i16 memory.
FNSTCW16m, FNSTCW16m,
/// This instruction implements FP_TO_SINT with the /// This instruction implements FP_TO_SINT with the
/// integer destination in memory and a FP reg source. This corresponds /// integer destination in memory and a FP reg source. This corresponds
/// to the X86::FIST*m instructions and the rounding mode change stuff. It /// to the X86::FIST*m instructions and the rounding mode change stuff. It
/// has two inputs (token chain and address) and two outputs (int value /// has two inputs (token chain and address) and two outputs (int value
/// and token chain). Memory VT specifies the type to store to. /// and token chain). Memory VT specifies the type to store to.
FP_TO_INT_IN_MEM, FP_TO_INT_IN_MEM,
/// This instruction implements SINT_TO_FP with the /// This instruction implements SINT_TO_FP with the
/// integer source in memory and FP reg result. This corresponds to the /// integer source in memory and FP reg result. This corresponds to the
/// X86::FILD*m instructions. It has two inputs (token chain and address) /// X86::FILD*m instructions. It has two inputs (token chain and address)
/// and two outputs (FP value and token chain). The integer source type is /// and two outputs (FP value and token chain). The integer source type is
/// specified by the memory VT. /// specified by the memory VT.
FILD, FILD,
/// This instruction implements a fp->int store from FP stack /// This instruction implements a fp->int store from FP stack
/// slots. This corresponds to the fist instruction. It takes a /// slots. This corresponds to the fist instruction. It takes a
/// chain operand, value to store, address, and glue. The memory VT /// chain operand, value to store, address, and glue. The memory VT
/// specifies the type to store as. /// specifies the type to store as.
FIST, FIST,
/// This instruction implements an extending load to FP stack slots. /// This instruction implements an extending load to FP stack slots.
/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
/// operand, and ptr to load from. The memory VT specifies the type to /// operand, and ptr to load from. The memory VT specifies the type to
/// load from. /// load from.
FLD, FLD,
/// This instruction implements a truncating store from FP stack /// This instruction implements a truncating store from FP stack
/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
/// chain operand, value to store, address, and glue. The memory VT /// chain operand, value to store, address, and glue. The memory VT
/// specifies the type to store as. /// specifies the type to store as.
FST, FST,
/// This instruction grabs the address of the next argument /// This instruction grabs the address of the next argument
/// from a va_list. (reads and modifies the va_list in memory) /// from a va_list. (reads and modifies the va_list in memory)
VAARG_64, VAARG_64,
// Vector truncating store with unsigned/signed saturation // Vector truncating store with unsigned/signed saturation
VTRUNCSTOREUS, VTRUNCSTORES, VTRUNCSTOREUS,
VTRUNCSTORES,
// Vector truncating masked store with unsigned/signed saturation // Vector truncating masked store with unsigned/signed saturation
VMTRUNCSTOREUS, VMTRUNCSTORES, VMTRUNCSTOREUS,
VMTRUNCSTORES,
// X86 specific gather and scatter // X86 specific gather and scatter
MGATHER, MSCATTER, MGATHER,
MSCATTER,
// WARNING: Do not add anything in the end unless you want the node to // WARNING: Do not add anything in the end unless you want the node to
// have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
// opcodes will be thought as target memory ops! // opcodes will be thought as target memory ops!
}; };
} // end namespace X86ISD } // end namespace X86ISD
/// Define some predicates that are used for node matching. /// Define some predicates that are used for node matching.
namespace X86 { namespace X86 {
/// Returns true if Elt is a constant zero or floating point constant +0.0. /// Returns true if Elt is a constant zero or floating point constant +0.0.
bool isZeroNode(SDValue Elt); bool isZeroNode(SDValue Elt);
/// Returns true of the given offset can be /// Returns true of the given offset can be
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