[AMDGPU] Add AGPRs to getRegClassForSizeOnBank

[foad]

Seems obviously fine. I assume you have a use for it!

[kerbowa]

In D79761#2031297, @foad wrote:

Seems obviously fine. I assume you have a use for it!

Yes, for mfma in globalisel.

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
   case AMDGPU::VGPRRegBankID:
     return getVGPRClassForBitWidth(std::max(32u, Size));
   case AMDGPU::VCCRegBankID:
     assert(Size == 1);
     return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
                     : &AMDGPU::SReg_64_XEXECRegClass;
   case AMDGPU::SGPRRegBankID:
     return getSGPRClassForBitWidth(std::max(32u, Size));
+  case AMDGPU::AGPRRegBankID:
+    return getAGPRClassForBitWidth(std::max(32u, Size));
   default:
     llvm_unreachable("unknown register bank");
   }
 }
 
 const TargetRegisterClass *
 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
                                          const MachineRegisterInfo &MRI) const {