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Differential D79567

[GlobalISel] Combine scalar unmerge(trunc)
ClosedPublic

Authored by gargaroff on May 7 2020, 4:29 AM.

Details

Reviewers
arsenm
aditya_nandakumar
volkan
Commits
rG052c962ced71: [GlobalISel] Combine scalar unmerge(trunc)
Summary

Combine unmerge(trunc) to enable other merge combines.
Without this combine, the scalar unmerge(trunc(merge))
pattern cannot be combined and easily lead to
hard-to-legalize merge/unmerge artifacts.

Diff Detail

Event Timeline

gargaroff created this revision.May 7 2020, 4:29 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 7 2020, 4:29 AM
Herald added subscribers: llvm-commits, kerbowa, rovka and 3 others. · View Herald Transcript
gargaroff added a comment.May 7 2020, 4:31 AM

Not sure whether this combine is desired. We need it for our out-of-tree backend, as otherwise there are quite a few cases with non-power-of-2 types which fail legalization due to non-combinable unmerge(trunc(merge)) patterns.

Harbormaster completed remote builds in B56050: Diff 262613.May 7 2020, 5:38 AM
gargaroff updated this revision to Diff 263132.May 11 2020, 3:09 AM

Rebase.

I didn't bother to move your vector unmerge(trunc) combine to the new tryFoldUnmergeCast for now, @arsenm. I plan to do that after some initial feedback though

Harbormaster completed remote builds in B56287: Diff 263132.May 11 2020, 4:15 AM
arsenm added inline comments.May 11 2020, 2:36 PM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
369

Needs example comment

370

Can set initial size to NewNumDefs and avoid push_back

529–531

Dead return

gargaroff updated this revision to Diff 263366.May 11 2020, 11:54 PM
gargaroff marked 3 inline comments as done.

Add example comment
Set initial size to NewNumDefs
Remove dead return
Move vector unmerge(trunc) combine to tryFoldUnmergeCast

Harbormaster completed remote builds in B56405: Diff 263366.May 12 2020, 1:02 AM
gargaroff added a comment.May 17 2020, 11:24 PM

@arsenm Is this good to go or do you have any other feedback?

gargaroff added a comment.May 28 2020, 12:32 AM

ping

arsenm accepted this revision.May 28 2020, 6:55 AM
arsenm added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
356–366

I think the diff is messed up and includes one of my recent patches now. I'm assuming much of this will disappear in the final version?

This revision is now accepted and ready to land.May 28 2020, 6:55 AM
gargaroff closed this revision.Jun 2 2020, 12:01 AM
gargaroff marked 2 inline comments as done.

052c962ced71c5130d709186b78c37a4adc59d66

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
356–366

Kind-of. I extracted both of our code to a new function to keep the code more readable in tryCombineMerges and to make it more easy to add other merge-cast combines, which is why most of it appears in this diff now. I'm going to land that as a separate commit though.

gargaroff mentioned this in rGb3c6a36dba56: [NFC] Move vector unmerge(trunc) combine to function.Jun 2 2020, 12:31 AM

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
132 lines
test/
CodeGen/
AArch64/
GlobalISel/
9 lines
AMDGPU/
GlobalISel/
24 lines
21 lines
69 lines
34 lines
1128 lines
36 lines
293 lines
24 lines

Diff 263366

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
} }
markInstAndDefDead(MI, *DefMI, DeadInsts); markInstAndDefDead(MI, *DefMI, DeadInsts);
return true; return true;
} }
return false; return false;
} }
static bool canFoldMergeOpcode(unsigned MergeOp, unsigned ConvertOp, bool tryFoldUnmergeCast(MachineInstr &MI, MachineInstr &CastMI,
LLT OpTy, LLT DestTy) { SmallVectorImpl<MachineInstr *> &DeadInsts,
SmallVectorImpl<Register> &UpdatedDefs) {
assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
const unsigned CastOpc = CastMI.getOpcode();
if (!isArtifactCast(CastOpc))
return false;
const unsigned NumDefs = MI.getNumOperands() - 1;
const Register CastSrcReg = CastMI.getOperand(1).getReg();
const LLT CastSrcTy = MRI.getType(CastSrcReg);
const LLT DestTy = MRI.getType(MI.getOperand(0).getReg());
const LLT SrcTy = MRI.getType(MI.getOperand(NumDefs).getReg());
const unsigned CastSrcSize = CastSrcTy.getSizeInBits();
const unsigned DestSize = DestTy.getSizeInBits();
if (CastOpc == TargetOpcode::G_TRUNC) {
if (SrcTy.isVector() && SrcTy.getScalarType() == DestTy.getScalarType()) {
// %1:_(<4 x s8>) = G_TRUNC %0(<4 x s32>)
// %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
// =>
// %6:_(s32), %7:_(s32), %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %0
// %2:_(s8) = G_TRUNC %6
// %3:_(s8) = G_TRUNC %7
// %4:_(s8) = G_TRUNC %8
// %5:_(s8) = G_TRUNC %9
arsenmUnsubmitted
Not Done
ReplyInline Actions

I think the diff is messed up and includes one of my recent patches now. I'm assuming much of this will disappear in the final version?

arsenm: I think the diff is messed up and includes one of my recent patches now. I'm assuming much of…
gargaroffAuthorUnsubmitted
Done
ReplyInline Actions

Kind-of. I extracted both of our code to a new function to keep the code more readable in tryCombineMerges and to make it more easy to add other merge-cast combines, which is why most of it appears in this diff now. I'm going to land that as a separate commit though.

gargaroff: Kind-of. I extracted both of our code to a new function to keep the code more readable in…
unsigned UnmergeNumElts =
DestTy.isVector() ? CastSrcTy.getNumElements() / NumDefs : 1;
LLT UnmergeTy = CastSrcTy.changeNumElements(UnmergeNumElts);
arsenmUnsubmitted
Done
ReplyInline Actions

Needs example comment

arsenm: Needs example comment
arsenmUnsubmitted
Done
ReplyInline Actions

Can set initial size to NewNumDefs and avoid push_back

arsenm: Can set initial size to NewNumDefs and avoid push_back
if (isInstUnsupported(
{TargetOpcode::G_UNMERGE_VALUES, {UnmergeTy, CastSrcTy}}))
return false;
Builder.setInstr(MI);
auto NewUnmerge = Builder.buildUnmerge(UnmergeTy, CastSrcReg);
SmallVector<Register, 8> Regs(NumDefs);
for (unsigned I = 0; I != NumDefs; ++I)
Builder.buildTrunc(MI.getOperand(I), NewUnmerge.getReg(I));
markInstAndDefDead(MI, CastMI, DeadInsts);
return true;
}
if (CastSrcTy.isScalar() && SrcTy.isScalar() && !DestTy.isVector()) {
// %1:_(s16) = G_TRUNC %0(s32)
// %2:_(s8), %3:_(s8) = G_UNMERGE_VALUES %1
// =>
// %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %0
// Unmerge(trunc) can be combined if the trunc source size is a multiple
// of the unmerge destination size
if (CastSrcSize % DestSize != 0)
return false;
// Check if the new unmerge is supported
if (isInstUnsupported(
{TargetOpcode::G_UNMERGE_VALUES, {DestTy, CastSrcTy}}))
return false;
// Gather the original destination registers and create new ones for the
// unused bits
const unsigned NewNumDefs = CastSrcSize / DestSize;
SmallVector<Register, 2> DstRegs(NewNumDefs);
for (unsigned Idx = 0; Idx < NewNumDefs; ++Idx) {
if (Idx < NumDefs)
DstRegs[Idx] = MI.getOperand(Idx).getReg();
else
DstRegs[Idx] = MRI.createGenericVirtualRegister(DestTy);
}
// Build new unmerge
Builder.setInstr(MI);
Builder.buildUnmerge(DstRegs, CastSrcReg);
UpdatedDefs.append(DstRegs.begin(), DstRegs.begin() + NumDefs);
markInstAndDefDead(MI, CastMI, DeadInsts);
return true;
}
}
// TODO: support combines with other casts as well
return false;
}
static bool canFoldMergeOpcode(unsigned MergeOp, unsigned ConvertOp, LLT OpTy,
LLT DestTy) {
// Check if we found a definition that is like G_MERGE_VALUES. // Check if we found a definition that is like G_MERGE_VALUES.
switch (MergeOp) { switch (MergeOp) {
default: default:
return false; return false;
case TargetOpcode::G_BUILD_VECTOR: case TargetOpcode::G_BUILD_VECTOR:
case TargetOpcode::G_MERGE_VALUES: case TargetOpcode::G_MERGE_VALUES:
// The convert operation that we will need to insert is // The convert operation that we will need to insert is
// going to convert the input of that type of instruction (scalar) // going to convert the input of that type of instruction (scalar)
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines bool tryCombineMerges(MachineInstr &MI,
unsigned SrcOp = SrcDef->getOpcode(); unsigned SrcOp = SrcDef->getOpcode();
if (isArtifactCast(SrcOp)) { if (isArtifactCast(SrcOp)) {
ConvertOp = SrcOp; ConvertOp = SrcOp;
MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI); MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI);
} }
if (!MergeI || !canFoldMergeOpcode(MergeI->getOpcode(), if (!MergeI || !canFoldMergeOpcode(MergeI->getOpcode(),
ConvertOp, OpTy, DestTy)) { ConvertOp, OpTy, DestTy)) {
if (ConvertOp == TargetOpcode::G_TRUNC && OpTy.isVector() && // We might have a chance to combine later by trying to combine
OpTy.getScalarType() == DestTy.getScalarType()) { // unmerge(cast) first
Register TruncSrc = SrcDef->getOperand(1).getReg(); return tryFoldUnmergeCast(MI, *SrcDef, DeadInsts, UpdatedDefs);
arsenmUnsubmitted
Done
ReplyInline Actions

Dead return

arsenm: Dead return
LLT TruncSrcTy = MRI.getType(TruncSrc);
// %1:_(<4 x s8>) = G_TRUNC %0(<4 x s32>)
// %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
// =>
// %6:_(s32), %7:_(s32), %8:_(s32), %9:_(s32) = G_UNMERGE_VALUES %0
// %2:_(s8) = G_TRUNC %6
// %3:_(s8) = G_TRUNC %7
// %4:_(s8) = G_TRUNC %8
// %5:_(s8) = G_TRUNC %9
unsigned UnmergeNumElts = DestTy.isVector() ?
TruncSrcTy.getNumElements() / NumDefs : 1;
LLT UnmergeTy = TruncSrcTy.changeNumElements(UnmergeNumElts);
if (isInstUnsupported(
{TargetOpcode::G_UNMERGE_VALUES, {UnmergeTy, TruncSrcTy}}))
return false;
Builder.setInstr(MI);
auto NewUnmerge = Builder.buildUnmerge(UnmergeTy, TruncSrc);
SmallVector<Register, 8> Regs(NumDefs);
for (unsigned I = 0; I != NumDefs; ++I)
Builder.buildTrunc(MI.getOperand(I), NewUnmerge.getReg(I));
markInstAndDefDead(MI, *SrcDef, DeadInsts);
return true;
}
return false;
} }
const unsigned NumMergeRegs = MergeI->getNumOperands() - 1; const unsigned NumMergeRegs = MergeI->getNumOperands() - 1;
if (NumMergeRegs < NumDefs) { if (NumMergeRegs < NumDefs) {
if (NumDefs % NumMergeRegs != 0) if (NumDefs % NumMergeRegs != 0)
return false; return false;
▲ Show 20 Lines • Show All 384 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir

Show All 17 Lines
--- ---
name: test_unmerge_s4 name: test_unmerge_s4
body: | body: |
bb.0: bb.0:
liveins: $w0 liveins: $w0
; CHECK-LABEL: name: test_unmerge_s4 ; CHECK-LABEL: name: test_unmerge_s4
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s8)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64) ; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64) ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s32) = COPY $w0 %0:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s4), %3:_(s4)= G_UNMERGE_VALUES %1 %2:_(s4), %3:_(s4)= G_UNMERGE_VALUES %1
%4:_(s64) = G_ANYEXT %2 %4:_(s64) = G_ANYEXT %2
%5:_(s64) = G_ANYEXT %3 %5:_(s64) = G_ANYEXT %3
$x0 = COPY %4 $x0 = COPY %4
$x1 = COPY %5 $x1 = COPY %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

Show First 20 Lines • Show All 923 Lines • ▼ Show 20 Lines
name: test_unmerge_values_s32_trunc_s96_of_merge_values_s192_s64 name: test_unmerge_values_s32_trunc_s96_of_merge_values_s192_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_unmerge_values_s32_trunc_s96_of_merge_values_s192_s64 ; CHECK-LABEL: name: test_unmerge_values_s32_trunc_s96_of_merge_values_s192_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV]](s192) ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
; CHECK: S_ENDPGM 0, implicit [[UV]](s32), implicit [[UV1]](s32), implicit [[UV2]](s32) ; CHECK: S_ENDPGM 0, implicit [[UV]](s32), implicit [[UV1]](s32), implicit [[UV2]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = COPY $vgpr4_vgpr5 %2:_(s64) = COPY $vgpr4_vgpr5
%3:_(s192) = G_MERGE_VALUES %0, %1, %2 %3:_(s192) = G_MERGE_VALUES %0, %1, %2
%4:_(s96) = G_TRUNC %3 %4:_(s96) = G_TRUNC %3
%5:_(s32), %6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %4 %5:_(s32), %6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %4
S_ENDPGM 0, implicit %5, implicit %6, implicit %7 S_ENDPGM 0, implicit %5, implicit %6, implicit %7
... ...
--- ---
name: test_unmerge_values_s16_trunc_s96_of_merge_values_s192_s64 name: test_unmerge_values_s16_trunc_s96_of_merge_values_s192_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: test_unmerge_values_s16_trunc_s96_of_merge_values_s192_s64 ; CHECK-LABEL: name: test_unmerge_values_s16_trunc_s96_of_merge_values_s192_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV]](s192) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32) ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16), implicit [[TRUNC4]](s16), implicit [[TRUNC5]](s16), implicit [[TRUNC6]](s16) ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16), implicit [[TRUNC4]](s16), implicit [[TRUNC5]](s16)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = COPY $vgpr4_vgpr5 %2:_(s64) = COPY $vgpr4_vgpr5
%3:_(s192) = G_MERGE_VALUES %0, %1, %2 %3:_(s192) = G_MERGE_VALUES %0, %1, %2
%4:_(s96) = G_TRUNC %3 %4:_(s96) = G_TRUNC %3
%5:_(s16), %6:_(s16), %7:_(s16), %8:_(s16), %9:_(s16), %10:_(s16) = G_UNMERGE_VALUES %4 %5:_(s16), %6:_(s16), %7:_(s16), %8:_(s16), %9:_(s16), %10:_(s16) = G_UNMERGE_VALUES %4
S_ENDPGM 0, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10 S_ENDPGM 0, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10
▲ Show 20 Lines • Show All 372 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines; VI-NEXT: s_setpc_b64 s[30:31]
%cvt = uitofp i8 %arg0 to float %cvt = uitofp i8 %arg0 to float
ret float %cvt ret float %cvt
} }
define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind { define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind {
; SI-LABEL: v_uitofp_v2i8_to_v2f32: ; SI-LABEL: v_uitofp_v2i8_to_v2f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; SI-NEXT: s_movk_i32 s4, 0xff ; SI-NEXT: s_movk_i32 s4, 0xff
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; SI-NEXT: v_and_b32_e32 v0, s4, v0 ; SI-NEXT: v_and_b32_e32 v0, s4, v0
; SI-NEXT: v_and_b32_e32 v1, s4, v1 ; SI-NEXT: v_and_b32_e32 v1, s4, v1
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: s_setpc_b64 s[30:31]
; ;
; VI-LABEL: v_uitofp_v2i8_to_v2f32: ; VI-LABEL: v_uitofp_v2i8_to_v2f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s4, 0xff ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_cvt_f32_ubyte0_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 ; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_and_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v0
; VI-NEXT: v_mov_b32_e32 v0, v2
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
%val = bitcast i16 %arg0 to <2 x i8> %val = bitcast i16 %arg0 to <2 x i8>
%cvt = uitofp <2 x i8> %val to <2 x float> %cvt = uitofp <2 x i8> %val to <2 x float>
ret <2 x float> %cvt ret <2 x float> %cvt
} }
define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind { define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind {
; SI-LABEL: v_uitofp_v3i8_to_v3f32: ; SI-LABEL: v_uitofp_v3i8_to_v3f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT: s_movk_i32 s4, 0xff ; SI-NEXT: s_movk_i32 s4, 0xff
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; SI-NEXT: v_and_b32_e32 v0, s4, v0 ; SI-NEXT: v_and_b32_e32 v0, s4, v0
; SI-NEXT: v_and_b32_e32 v1, s4, v1 ; SI-NEXT: v_and_b32_e32 v1, s4, v1
; SI-NEXT: v_and_b32_e32 v2, s4, v2 ; SI-NEXT: v_and_b32_e32 v2, s4, v2
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1
; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2 ; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: s_setpc_b64 s[30:31]
; ;
; VI-LABEL: v_uitofp_v3i8_to_v3f32: ; VI-LABEL: v_uitofp_v3i8_to_v3f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_movk_i32 s4, 0xff ; VI-NEXT: s_movk_i32 s4, 0xff
; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_and_b32_sdwa v1, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 ; VI-NEXT: v_cvt_f32_ubyte0_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0 ; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 ; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_mov_b32_e32 v0, v3 ; VI-NEXT: v_mov_b32_e32 v0, v3
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc i32 %arg0 to i24 %trunc = trunc i32 %arg0 to i24
%val = bitcast i24 %trunc to <3 x i8> %val = bitcast i24 %trunc to <3 x i8>
%cvt = uitofp <3 x i8> %val to <3 x float> %cvt = uitofp <3 x i8> %val to <3 x float>
ret <3 x float> %cvt ret <3 x float> %cvt
} }
▲ Show 20 Lines • Show All 922 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Lines
--- ---
name: test_bitcast_s24_to_v3s8 name: test_bitcast_s24_to_v3s8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_bitcast_s24_to_v3s8 ; CHECK-LABEL: name: test_bitcast_s24_to_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192) ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0 %1:_(s24) = G_TRUNC %0
%2:_(<3 x s8>) = G_BITCAST %1 %2:_(<3 x s8>) = G_BITCAST %1
%3:_(<3 x s32>) = G_ANYEXT %2 %3:_(<3 x s32>) = G_ANYEXT %2
$vgpr0_vgpr1_vgpr2 = COPY %3 $vgpr0_vgpr1_vgpr2 = COPY %3
... ...
--- ---
name: test_bitcast_s48_to_v3s16 name: test_bitcast_s48_to_v3s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_bitcast_s48_to_v3s16 ; CHECK-LABEL: name: test_bitcast_s48_to_v3s16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV3]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0 ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) ; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>) ; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>) ; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0 %1:_(s48) = G_TRUNC %0
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
--- ---
name: test_bitcast_s16_to_v2s8 name: test_bitcast_s16_to_v2s8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_bitcast_s16_to_v2s8 ; CHECK-LABEL: name: test_bitcast_s16_to_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C]](s16) ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(<2 x s8>) = G_BITCAST %1 %2:_(<2 x s8>) = G_BITCAST %1
%3:_(<2 x s32>) = G_ANYEXT %2 %3:_(<2 x s32>) = G_ANYEXT %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
Show All 25 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir

Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines
name: test_freeze_s1056 name: test_freeze_s1056
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_freeze_s1056 ; CHECK-LABEL: name: test_freeze_s1056
; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s512) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s512)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32)
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
; CHECK: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV9]](s32)
; CHECK: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV10]](s32), [[UV11]](s32)
; CHECK: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32)
; CHECK: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV14]](s32), [[UV15]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV8:%[0-9]+]]:_(s2112) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64) ; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s1056) = G_TRUNC [[MV8]](s2112) ; CHECK: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s1056) ; CHECK: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[MV9:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[UV16]](s32), [[UV17]](s32), [[UV18]](s32), [[UV19]](s32), [[UV20]](s32), [[UV21]](s32), [[UV22]](s32), [[UV23]](s32), [[UV24]](s32), [[UV25]](s32), [[UV26]](s32), [[UV27]](s32), [[UV28]](s32), [[UV29]](s32), [[UV30]](s32), [[UV31]](s32), [[UV32]](s32), [[UV33]](s32), [[UV34]](s32), [[UV35]](s32), [[UV36]](s32), [[UV37]](s32), [[UV38]](s32), [[UV39]](s32), [[UV40]](s32), [[UV41]](s32), [[UV42]](s32), [[UV43]](s32), [[UV44]](s32), [[UV45]](s32), [[UV46]](s32), [[UV47]](s32) ; CHECK: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[MV10:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[UV48]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32) ; CHECK: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32), [[UV4]](s32), [[UV5]](s32), [[UV6]](s32), [[UV7]](s32), [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32), [[UV12]](s32), [[UV13]](s32), [[UV14]](s32), [[UV15]](s32), [[UV16]](s32), [[UV17]](s32), [[UV18]](s32), [[UV19]](s32), [[UV20]](s32), [[UV21]](s32), [[UV22]](s32), [[UV23]](s32), [[UV24]](s32), [[UV25]](s32), [[UV26]](s32), [[UV27]](s32), [[UV28]](s32), [[UV29]](s32), [[UV30]](s32), [[UV31]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[UV32]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32)
; CHECK: [[DEF2:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF ; CHECK: [[DEF2:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF
; CHECK: [[FREEZE:%[0-9]+]]:_(s1024) = G_FREEZE [[MV9]] ; CHECK: [[FREEZE:%[0-9]+]]:_(s1024) = G_FREEZE [[MV]]
; CHECK: [[FREEZE1:%[0-9]+]]:_(s1024) = G_FREEZE [[MV10]] ; CHECK: [[FREEZE1:%[0-9]+]]:_(s1024) = G_FREEZE [[MV1]]
; CHECK: [[MV11:%[0-9]+]]:_(s33792) = G_MERGE_VALUES [[FREEZE]](s1024), [[FREEZE1]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024) ; CHECK: [[MV2:%[0-9]+]]:_(s33792) = G_MERGE_VALUES [[FREEZE]](s1024), [[FREEZE1]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024), [[DEF2]](s1024)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1056) = G_TRUNC [[MV11]](s33792) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1056) = G_TRUNC [[MV2]](s33792)
; CHECK: S_NOP 0, implicit [[TRUNC1]](s1056) ; CHECK: S_NOP 0, implicit [[TRUNC]](s1056)
%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 %0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:_(s1056) = G_ANYEXT %0 %1:_(s1056) = G_ANYEXT %0
%2:_(s1056) = G_FREEZE %1 %2:_(s1056) = G_FREEZE %1
S_NOP 0, implicit %2 S_NOP 0, implicit %2
... ...
--- ---
name: test_freeze_s2048 name: test_freeze_s2048
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir

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name: test_merge_s68_s17_s17_s17_s17 name: test_merge_s68_s17_s17_s17_s17
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s68_s17_s17_s17_s17 ; CHECK-LABEL: name: test_merge_s68_s17_s17_s17_s17
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32) ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]] ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C4]](s32) ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL1]] ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32) ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s1088) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64) ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s544) = G_TRUNC [[MV1]](s1088) ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s544) ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C4]](s32) ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]] ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C5]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY4]](s32) ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]] ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32) ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]] ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY8]](s32) ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C6]](s32) ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]] ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY10]](s32) ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C8]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C7]](s32) ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]] ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY12]](s32) ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C9]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32) ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]] ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY14]](s32) ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 ; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C10]](s32)
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C5]]
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY16]](s32)
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C5]]
; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY18]](s32)
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C5]]
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY20]](s32)
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C5]]
; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY22]](s32)
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C5]]
; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY24]](s32)
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C5]]
; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY26]](s32)
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C5]]
; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY28]](s32)
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C5]]
; CHECK: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY30]](s32)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C5]]
; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY32]](s32)
; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C5]]
; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY34]](s32)
; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C5]]
; CHECK: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY36]](s32)
; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C5]]
; CHECK: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY38]](s32)
; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C5]]
; CHECK: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY40]](s32)
; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C5]]
; CHECK: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY42]](s32)
; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C5]]
; CHECK: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY44]](s32)
; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C5]]
; CHECK: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY46]](s32)
; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C5]]
; CHECK: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY48]](s32)
; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C5]]
; CHECK: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY50]](s32)
; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C5]]
; CHECK: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY52]](s32)
; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C5]]
; CHECK: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY54]](s32)
; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C5]]
; CHECK: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY56]](s32)
; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C5]]
; CHECK: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY58]](s32)
; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C5]]
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY60]](s32)
; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C5]]
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY62]](s32)
; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY65]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY64]], [[SHL2]]
; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY67]], [[C4]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY66]], [[SHL3]]
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
; CHECK: [[MV3:%[0-9]+]]:_(s1088) = G_MERGE_VALUES [[MV2]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s544) = G_TRUNC [[MV3]](s1088)
; CHECK: [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC1]](s544)
; CHECK: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[UV17]], [[C4]](s32)
; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY69:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY69]], [[C5]]
; CHECK: [[LSHR32:%[0-9]+]]:_(s32) = G_LSHR [[AND30]], [[COPY68]](s32)
; CHECK: [[COPY70:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY71:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY71]], [[C5]]
; CHECK: [[LSHR33:%[0-9]+]]:_(s32) = G_LSHR [[AND31]], [[COPY70]](s32)
; CHECK: [[COPY72:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY73:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY73]], [[C5]]
; CHECK: [[LSHR34:%[0-9]+]]:_(s32) = G_LSHR [[AND32]], [[COPY72]](s32)
; CHECK: [[COPY74:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY75:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY75]], [[C5]]
; CHECK: [[LSHR35:%[0-9]+]]:_(s32) = G_LSHR [[AND33]], [[COPY74]](s32)
; CHECK: [[COPY76:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY77:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY77]], [[C5]]
; CHECK: [[LSHR36:%[0-9]+]]:_(s32) = G_LSHR [[AND34]], [[COPY76]](s32)
; CHECK: [[COPY78:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY79:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY79]], [[C5]]
; CHECK: [[LSHR37:%[0-9]+]]:_(s32) = G_LSHR [[AND35]], [[COPY78]](s32)
; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY81]], [[C5]]
; CHECK: [[LSHR38:%[0-9]+]]:_(s32) = G_LSHR [[AND36]], [[COPY80]](s32)
; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY83]], [[C5]]
; CHECK: [[LSHR39:%[0-9]+]]:_(s32) = G_LSHR [[AND37]], [[COPY82]](s32)
; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY85]], [[C5]]
; CHECK: [[LSHR40:%[0-9]+]]:_(s32) = G_LSHR [[AND38]], [[COPY84]](s32)
; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY87]], [[C5]]
; CHECK: [[LSHR41:%[0-9]+]]:_(s32) = G_LSHR [[AND39]], [[COPY86]](s32)
; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY89:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY89]], [[C5]]
; CHECK: [[LSHR42:%[0-9]+]]:_(s32) = G_LSHR [[AND40]], [[COPY88]](s32)
; CHECK: [[COPY90:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY91:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY91]], [[C5]]
; CHECK: [[LSHR43:%[0-9]+]]:_(s32) = G_LSHR [[AND41]], [[COPY90]](s32)
; CHECK: [[COPY92:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY93:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY93]], [[C5]]
; CHECK: [[LSHR44:%[0-9]+]]:_(s32) = G_LSHR [[AND42]], [[COPY92]](s32)
; CHECK: [[COPY94:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY95:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY95]], [[C5]]
; CHECK: [[LSHR45:%[0-9]+]]:_(s32) = G_LSHR [[AND43]], [[COPY94]](s32)
; CHECK: [[COPY96:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY97:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY97]], [[C5]]
; CHECK: [[LSHR46:%[0-9]+]]:_(s32) = G_LSHR [[AND44]], [[COPY96]](s32)
; CHECK: [[COPY98:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY99:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY99]], [[C5]]
; CHECK: [[LSHR47:%[0-9]+]]:_(s32) = G_LSHR [[AND45]], [[COPY98]](s32)
; CHECK: [[COPY100:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY101:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY101]], [[C5]]
; CHECK: [[LSHR48:%[0-9]+]]:_(s32) = G_LSHR [[AND46]], [[COPY100]](s32)
; CHECK: [[COPY102:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY103:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY103]], [[C5]]
; CHECK: [[LSHR49:%[0-9]+]]:_(s32) = G_LSHR [[AND47]], [[COPY102]](s32)
; CHECK: [[COPY104:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY105:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY105]], [[C5]]
; CHECK: [[LSHR50:%[0-9]+]]:_(s32) = G_LSHR [[AND48]], [[COPY104]](s32)
; CHECK: [[COPY106:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY107:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY107]], [[C5]]
; CHECK: [[LSHR51:%[0-9]+]]:_(s32) = G_LSHR [[AND49]], [[COPY106]](s32)
; CHECK: [[COPY108:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY109:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY109]], [[C5]]
; CHECK: [[LSHR52:%[0-9]+]]:_(s32) = G_LSHR [[AND50]], [[COPY108]](s32)
; CHECK: [[COPY110:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY111:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY111]], [[C5]]
; CHECK: [[LSHR53:%[0-9]+]]:_(s32) = G_LSHR [[AND51]], [[COPY110]](s32)
; CHECK: [[COPY112:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY113:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY113]], [[C5]]
; CHECK: [[LSHR54:%[0-9]+]]:_(s32) = G_LSHR [[AND52]], [[COPY112]](s32)
; CHECK: [[COPY114:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY115:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY115]], [[C5]]
; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[AND53]], [[COPY114]](s32)
; CHECK: [[COPY116:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY117:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY117]], [[C5]]
; CHECK: [[LSHR56:%[0-9]+]]:_(s32) = G_LSHR [[AND54]], [[COPY116]](s32)
; CHECK: [[COPY118:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY119:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY119]], [[C5]]
; CHECK: [[LSHR57:%[0-9]+]]:_(s32) = G_LSHR [[AND55]], [[COPY118]](s32)
; CHECK: [[COPY120:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY121:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY121]], [[C5]]
; CHECK: [[LSHR58:%[0-9]+]]:_(s32) = G_LSHR [[AND56]], [[COPY120]](s32)
; CHECK: [[COPY122:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY123:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY123]], [[C5]]
; CHECK: [[LSHR59:%[0-9]+]]:_(s32) = G_LSHR [[AND57]], [[COPY122]](s32)
; CHECK: [[COPY124:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY125:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY125]], [[C5]]
; CHECK: [[LSHR60:%[0-9]+]]:_(s32) = G_LSHR [[AND58]], [[COPY124]](s32)
; CHECK: [[COPY126:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY127:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY127]], [[C5]]
; CHECK: [[LSHR61:%[0-9]+]]:_(s32) = G_LSHR [[AND59]], [[COPY126]](s32)
; CHECK: [[COPY128:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY129:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY129]], [[C4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY128]], [[SHL4]]
; CHECK: [[COPY130:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY131:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY131]], [[C4]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY130]], [[SHL5]]
; CHECK: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK: [[MV5:%[0-9]+]]:_(s1088) = G_MERGE_VALUES [[MV4]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s544) = G_TRUNC [[MV5]](s1088)
; CHECK: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC2]](s544)
; CHECK: [[LSHR62:%[0-9]+]]:_(s32) = G_LSHR [[UV34]], [[C4]](s32)
; CHECK: [[COPY132:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY133:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY133]], [[C5]]
; CHECK: [[LSHR63:%[0-9]+]]:_(s32) = G_LSHR [[AND60]], [[COPY132]](s32)
; CHECK: [[COPY134:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY135:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY135]], [[C5]]
; CHECK: [[LSHR64:%[0-9]+]]:_(s32) = G_LSHR [[AND61]], [[COPY134]](s32)
; CHECK: [[COPY136:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY137:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY137]], [[C5]]
; CHECK: [[LSHR65:%[0-9]+]]:_(s32) = G_LSHR [[AND62]], [[COPY136]](s32)
; CHECK: [[COPY138:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY139:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY139]], [[C5]]
; CHECK: [[LSHR66:%[0-9]+]]:_(s32) = G_LSHR [[AND63]], [[COPY138]](s32)
; CHECK: [[COPY140:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY141:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[COPY141]], [[C5]]
; CHECK: [[LSHR67:%[0-9]+]]:_(s32) = G_LSHR [[AND64]], [[COPY140]](s32)
; CHECK: [[COPY142:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY143:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND65:%[0-9]+]]:_(s32) = G_AND [[COPY143]], [[C5]]
; CHECK: [[LSHR68:%[0-9]+]]:_(s32) = G_LSHR [[AND65]], [[COPY142]](s32)
; CHECK: [[COPY144:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY145:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND66:%[0-9]+]]:_(s32) = G_AND [[COPY145]], [[C5]]
; CHECK: [[LSHR69:%[0-9]+]]:_(s32) = G_LSHR [[AND66]], [[COPY144]](s32)
; CHECK: [[COPY146:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY147:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND67:%[0-9]+]]:_(s32) = G_AND [[COPY147]], [[C5]]
; CHECK: [[LSHR70:%[0-9]+]]:_(s32) = G_LSHR [[AND67]], [[COPY146]](s32)
; CHECK: [[COPY148:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY149:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND68:%[0-9]+]]:_(s32) = G_AND [[COPY149]], [[C5]]
; CHECK: [[LSHR71:%[0-9]+]]:_(s32) = G_LSHR [[AND68]], [[COPY148]](s32)
; CHECK: [[COPY150:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY151:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND69:%[0-9]+]]:_(s32) = G_AND [[COPY151]], [[C5]]
; CHECK: [[LSHR72:%[0-9]+]]:_(s32) = G_LSHR [[AND69]], [[COPY150]](s32)
; CHECK: [[COPY152:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY153:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND70:%[0-9]+]]:_(s32) = G_AND [[COPY153]], [[C5]]
; CHECK: [[LSHR73:%[0-9]+]]:_(s32) = G_LSHR [[AND70]], [[COPY152]](s32)
; CHECK: [[COPY154:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY155:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND71:%[0-9]+]]:_(s32) = G_AND [[COPY155]], [[C5]]
; CHECK: [[LSHR74:%[0-9]+]]:_(s32) = G_LSHR [[AND71]], [[COPY154]](s32)
; CHECK: [[COPY156:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY157:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND72:%[0-9]+]]:_(s32) = G_AND [[COPY157]], [[C5]]
; CHECK: [[LSHR75:%[0-9]+]]:_(s32) = G_LSHR [[AND72]], [[COPY156]](s32)
; CHECK: [[COPY158:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY159:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND73:%[0-9]+]]:_(s32) = G_AND [[COPY159]], [[C5]]
; CHECK: [[LSHR76:%[0-9]+]]:_(s32) = G_LSHR [[AND73]], [[COPY158]](s32)
; CHECK: [[COPY160:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY161:%[0-9]+]]:_(s32) = COPY [[UV34]](s32)
; CHECK: [[AND74:%[0-9]+]]:_(s32) = G_AND [[COPY161]], [[C5]]
; CHECK: [[LSHR77:%[0-9]+]]:_(s32) = G_LSHR [[AND74]], [[COPY160]](s32)
; CHECK: [[COPY162:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY163:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND75:%[0-9]+]]:_(s32) = G_AND [[COPY163]], [[C5]]
; CHECK: [[LSHR78:%[0-9]+]]:_(s32) = G_LSHR [[AND75]], [[COPY162]](s32)
; CHECK: [[COPY164:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY165:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND76:%[0-9]+]]:_(s32) = G_AND [[COPY165]], [[C5]]
; CHECK: [[LSHR79:%[0-9]+]]:_(s32) = G_LSHR [[AND76]], [[COPY164]](s32)
; CHECK: [[COPY166:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY167:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND77:%[0-9]+]]:_(s32) = G_AND [[COPY167]], [[C5]]
; CHECK: [[LSHR80:%[0-9]+]]:_(s32) = G_LSHR [[AND77]], [[COPY166]](s32)
; CHECK: [[COPY168:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY169:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND78:%[0-9]+]]:_(s32) = G_AND [[COPY169]], [[C5]]
; CHECK: [[LSHR81:%[0-9]+]]:_(s32) = G_LSHR [[AND78]], [[COPY168]](s32)
; CHECK: [[COPY170:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY171:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND79:%[0-9]+]]:_(s32) = G_AND [[COPY171]], [[C5]]
; CHECK: [[LSHR82:%[0-9]+]]:_(s32) = G_LSHR [[AND79]], [[COPY170]](s32)
; CHECK: [[COPY172:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY173:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND80:%[0-9]+]]:_(s32) = G_AND [[COPY173]], [[C5]]
; CHECK: [[LSHR83:%[0-9]+]]:_(s32) = G_LSHR [[AND80]], [[COPY172]](s32)
; CHECK: [[COPY174:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY175:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND81:%[0-9]+]]:_(s32) = G_AND [[COPY175]], [[C5]]
; CHECK: [[LSHR84:%[0-9]+]]:_(s32) = G_LSHR [[AND81]], [[COPY174]](s32)
; CHECK: [[COPY176:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY177:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND82:%[0-9]+]]:_(s32) = G_AND [[COPY177]], [[C5]]
; CHECK: [[LSHR85:%[0-9]+]]:_(s32) = G_LSHR [[AND82]], [[COPY176]](s32)
; CHECK: [[COPY178:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY179:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND83:%[0-9]+]]:_(s32) = G_AND [[COPY179]], [[C5]]
; CHECK: [[LSHR86:%[0-9]+]]:_(s32) = G_LSHR [[AND83]], [[COPY178]](s32)
; CHECK: [[COPY180:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY181:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND84:%[0-9]+]]:_(s32) = G_AND [[COPY181]], [[C5]]
; CHECK: [[LSHR87:%[0-9]+]]:_(s32) = G_LSHR [[AND84]], [[COPY180]](s32)
; CHECK: [[COPY182:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY183:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND85:%[0-9]+]]:_(s32) = G_AND [[COPY183]], [[C5]]
; CHECK: [[LSHR88:%[0-9]+]]:_(s32) = G_LSHR [[AND85]], [[COPY182]](s32)
; CHECK: [[COPY184:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY185:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND86:%[0-9]+]]:_(s32) = G_AND [[COPY185]], [[C5]]
; CHECK: [[LSHR89:%[0-9]+]]:_(s32) = G_LSHR [[AND86]], [[COPY184]](s32)
; CHECK: [[COPY186:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY187:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND87:%[0-9]+]]:_(s32) = G_AND [[COPY187]], [[C5]]
; CHECK: [[LSHR90:%[0-9]+]]:_(s32) = G_LSHR [[AND87]], [[COPY186]](s32)
; CHECK: [[COPY188:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY189:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND88:%[0-9]+]]:_(s32) = G_AND [[COPY189]], [[C5]]
; CHECK: [[LSHR91:%[0-9]+]]:_(s32) = G_LSHR [[AND88]], [[COPY188]](s32)
; CHECK: [[COPY190:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY191:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32)
; CHECK: [[AND89:%[0-9]+]]:_(s32) = G_AND [[COPY191]], [[C5]]
; CHECK: [[LSHR92:%[0-9]+]]:_(s32) = G_LSHR [[AND89]], [[COPY190]](s32)
; CHECK: [[COPY192:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY193:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY193]], [[C4]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY192]], [[SHL6]]
; CHECK: [[COPY194:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[COPY195:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY195]], [[C4]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[COPY194]], [[SHL7]]
; CHECK: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)
; CHECK: [[MV7:%[0-9]+]]:_(s1088) = G_MERGE_VALUES [[MV6]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s544) = G_TRUNC [[MV7]](s1088)
; CHECK: [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32), [[UV64:%[0-9]+]]:_(s32), [[UV65:%[0-9]+]]:_(s32), [[UV66:%[0-9]+]]:_(s32), [[UV67:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC3]](s544)
; CHECK: [[LSHR93:%[0-9]+]]:_(s32) = G_LSHR [[UV51]], [[C4]](s32)
; CHECK: [[COPY196:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY197:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND90:%[0-9]+]]:_(s32) = G_AND [[COPY197]], [[C5]]
; CHECK: [[LSHR94:%[0-9]+]]:_(s32) = G_LSHR [[AND90]], [[COPY196]](s32)
; CHECK: [[COPY198:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY199:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND91:%[0-9]+]]:_(s32) = G_AND [[COPY199]], [[C5]]
; CHECK: [[LSHR95:%[0-9]+]]:_(s32) = G_LSHR [[AND91]], [[COPY198]](s32)
; CHECK: [[COPY200:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY201:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND92:%[0-9]+]]:_(s32) = G_AND [[COPY201]], [[C5]]
; CHECK: [[LSHR96:%[0-9]+]]:_(s32) = G_LSHR [[AND92]], [[COPY200]](s32)
; CHECK: [[COPY202:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY203:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND93:%[0-9]+]]:_(s32) = G_AND [[COPY203]], [[C5]]
; CHECK: [[LSHR97:%[0-9]+]]:_(s32) = G_LSHR [[AND93]], [[COPY202]](s32)
; CHECK: [[COPY204:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY205:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND94:%[0-9]+]]:_(s32) = G_AND [[COPY205]], [[C5]]
; CHECK: [[LSHR98:%[0-9]+]]:_(s32) = G_LSHR [[AND94]], [[COPY204]](s32)
; CHECK: [[COPY206:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY207:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND95:%[0-9]+]]:_(s32) = G_AND [[COPY207]], [[C5]]
; CHECK: [[LSHR99:%[0-9]+]]:_(s32) = G_LSHR [[AND95]], [[COPY206]](s32)
; CHECK: [[COPY208:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY209:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND96:%[0-9]+]]:_(s32) = G_AND [[COPY209]], [[C5]]
; CHECK: [[LSHR100:%[0-9]+]]:_(s32) = G_LSHR [[AND96]], [[COPY208]](s32)
; CHECK: [[COPY210:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY211:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND97:%[0-9]+]]:_(s32) = G_AND [[COPY211]], [[C5]]
; CHECK: [[LSHR101:%[0-9]+]]:_(s32) = G_LSHR [[AND97]], [[COPY210]](s32)
; CHECK: [[COPY212:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY213:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND98:%[0-9]+]]:_(s32) = G_AND [[COPY213]], [[C5]]
; CHECK: [[LSHR102:%[0-9]+]]:_(s32) = G_LSHR [[AND98]], [[COPY212]](s32)
; CHECK: [[COPY214:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY215:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND99:%[0-9]+]]:_(s32) = G_AND [[COPY215]], [[C5]]
; CHECK: [[LSHR103:%[0-9]+]]:_(s32) = G_LSHR [[AND99]], [[COPY214]](s32)
; CHECK: [[COPY216:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY217:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND100:%[0-9]+]]:_(s32) = G_AND [[COPY217]], [[C5]]
; CHECK: [[LSHR104:%[0-9]+]]:_(s32) = G_LSHR [[AND100]], [[COPY216]](s32)
; CHECK: [[COPY218:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY219:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND101:%[0-9]+]]:_(s32) = G_AND [[COPY219]], [[C5]]
; CHECK: [[LSHR105:%[0-9]+]]:_(s32) = G_LSHR [[AND101]], [[COPY218]](s32)
; CHECK: [[COPY220:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY221:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND102:%[0-9]+]]:_(s32) = G_AND [[COPY221]], [[C5]]
; CHECK: [[LSHR106:%[0-9]+]]:_(s32) = G_LSHR [[AND102]], [[COPY220]](s32)
; CHECK: [[COPY222:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY223:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND103:%[0-9]+]]:_(s32) = G_AND [[COPY223]], [[C5]]
; CHECK: [[LSHR107:%[0-9]+]]:_(s32) = G_LSHR [[AND103]], [[COPY222]](s32)
; CHECK: [[COPY224:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY225:%[0-9]+]]:_(s32) = COPY [[UV51]](s32)
; CHECK: [[AND104:%[0-9]+]]:_(s32) = G_AND [[COPY225]], [[C5]]
; CHECK: [[LSHR108:%[0-9]+]]:_(s32) = G_LSHR [[AND104]], [[COPY224]](s32)
; CHECK: [[COPY226:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY227:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND105:%[0-9]+]]:_(s32) = G_AND [[COPY227]], [[C5]]
; CHECK: [[LSHR109:%[0-9]+]]:_(s32) = G_LSHR [[AND105]], [[COPY226]](s32)
; CHECK: [[COPY228:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[COPY229:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND106:%[0-9]+]]:_(s32) = G_AND [[COPY229]], [[C5]]
; CHECK: [[LSHR110:%[0-9]+]]:_(s32) = G_LSHR [[AND106]], [[COPY228]](s32)
; CHECK: [[COPY230:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY231:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND107:%[0-9]+]]:_(s32) = G_AND [[COPY231]], [[C5]]
; CHECK: [[LSHR111:%[0-9]+]]:_(s32) = G_LSHR [[AND107]], [[COPY230]](s32)
; CHECK: [[COPY232:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY233:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND108:%[0-9]+]]:_(s32) = G_AND [[COPY233]], [[C5]]
; CHECK: [[LSHR112:%[0-9]+]]:_(s32) = G_LSHR [[AND108]], [[COPY232]](s32)
; CHECK: [[COPY234:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[COPY235:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND109:%[0-9]+]]:_(s32) = G_AND [[COPY235]], [[C5]]
; CHECK: [[LSHR113:%[0-9]+]]:_(s32) = G_LSHR [[AND109]], [[COPY234]](s32)
; CHECK: [[COPY236:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY237:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND110:%[0-9]+]]:_(s32) = G_AND [[COPY237]], [[C5]]
; CHECK: [[LSHR114:%[0-9]+]]:_(s32) = G_LSHR [[AND110]], [[COPY236]](s32)
; CHECK: [[COPY238:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY239:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND111:%[0-9]+]]:_(s32) = G_AND [[COPY239]], [[C5]]
; CHECK: [[LSHR115:%[0-9]+]]:_(s32) = G_LSHR [[AND111]], [[COPY238]](s32)
; CHECK: [[COPY240:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY241:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND112:%[0-9]+]]:_(s32) = G_AND [[COPY241]], [[C5]]
; CHECK: [[LSHR116:%[0-9]+]]:_(s32) = G_LSHR [[AND112]], [[COPY240]](s32)
; CHECK: [[COPY242:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY243:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND113:%[0-9]+]]:_(s32) = G_AND [[COPY243]], [[C5]]
; CHECK: [[LSHR117:%[0-9]+]]:_(s32) = G_LSHR [[AND113]], [[COPY242]](s32)
; CHECK: [[COPY244:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[COPY245:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND114:%[0-9]+]]:_(s32) = G_AND [[COPY245]], [[C5]]
; CHECK: [[LSHR118:%[0-9]+]]:_(s32) = G_LSHR [[AND114]], [[COPY244]](s32)
; CHECK: [[COPY246:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[COPY247:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND115:%[0-9]+]]:_(s32) = G_AND [[COPY247]], [[C5]]
; CHECK: [[LSHR119:%[0-9]+]]:_(s32) = G_LSHR [[AND115]], [[COPY246]](s32)
; CHECK: [[COPY248:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[COPY249:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND116:%[0-9]+]]:_(s32) = G_AND [[COPY249]], [[C5]]
; CHECK: [[LSHR120:%[0-9]+]]:_(s32) = G_LSHR [[AND116]], [[COPY248]](s32)
; CHECK: [[COPY250:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; CHECK: [[COPY251:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND117:%[0-9]+]]:_(s32) = G_AND [[COPY251]], [[C5]]
; CHECK: [[LSHR121:%[0-9]+]]:_(s32) = G_LSHR [[AND117]], [[COPY250]](s32)
; CHECK: [[COPY252:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[COPY253:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND118:%[0-9]+]]:_(s32) = G_AND [[COPY253]], [[C5]]
; CHECK: [[LSHR122:%[0-9]+]]:_(s32) = G_LSHR [[AND118]], [[COPY252]](s32)
; CHECK: [[COPY254:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[COPY255:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32)
; CHECK: [[AND119:%[0-9]+]]:_(s32) = G_AND [[COPY255]], [[C5]]
; CHECK: [[LSHR123:%[0-9]+]]:_(s32) = G_LSHR [[AND119]], [[COPY254]](s32)
; CHECK: [[COPY256:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND120:%[0-9]+]]:_(s32) = G_AND [[COPY256]], [[C1]]
; CHECK: [[COPY257:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[AND121:%[0-9]+]]:_(s32) = G_AND [[COPY257]], [[C1]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND121]], [[C1]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND120]], [[SHL8]]
; CHECK: [[COPY258:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[AND122:%[0-9]+]]:_(s32) = G_AND [[COPY258]], [[C1]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND122]], [[C2]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]] ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
; CHECK: [[COPY259:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND123:%[0-9]+]]:_(s32) = G_AND [[COPY259]], [[C1]] ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND123]], [[C3]](s32) ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C11]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]] ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
; CHECK: [[COPY260:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32) ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND124:%[0-9]+]]:_(s32) = G_AND [[COPY260]], [[C1]] ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND124]], [[C6]](s32) ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C12]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]] ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CHECK: [[COPY261:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32) ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND125:%[0-9]+]]:_(s32) = G_AND [[COPY261]], [[C1]] ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND125]], [[C7]](s32) ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C13]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]] ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
; CHECK: [[COPY262:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32) ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND126:%[0-9]+]]:_(s32) = G_AND [[COPY262]], [[C1]] ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND126]], [[C8]](s32) ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C14]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]] ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK: [[COPY263:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32) ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND127:%[0-9]+]]:_(s32) = G_AND [[COPY263]], [[C1]] ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND127]], [[C9]](s32) ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C15]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]] ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CHECK: [[COPY264:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32) ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND128:%[0-9]+]]:_(s32) = G_AND [[COPY264]], [[C1]] ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND128]], [[C10]](s32) ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C16]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]] ; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; CHECK: [[COPY265:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32) ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND129:%[0-9]+]]:_(s32) = G_AND [[COPY265]], [[C1]] ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C1]]
; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND129]], [[C11]](s32) ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C17]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]] ; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
; CHECK: [[COPY266:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32) ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND130:%[0-9]+]]:_(s32) = G_AND [[COPY266]], [[C1]] ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C1]]
; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND130]], [[C12]](s32) ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C18]](s32)
; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]] ; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CHECK: [[COPY267:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32) ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND131:%[0-9]+]]:_(s32) = G_AND [[COPY267]], [[C1]] ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C1]]
; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND131]], [[C13]](s32) ; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C19]](s32)
; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]] ; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
; CHECK: [[COPY268:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32) ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND132:%[0-9]+]]:_(s32) = G_AND [[COPY268]], [[C1]] ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C1]]
; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND132]], [[C14]](s32) ; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C20]](s32)
; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]] ; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
; CHECK: [[COPY269:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32) ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND133:%[0-9]+]]:_(s32) = G_AND [[COPY269]], [[C1]] ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C1]]
; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND133]], [[C15]](s32) ; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C21]](s32)
; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]] ; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; CHECK: [[COPY270:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32) ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND134:%[0-9]+]]:_(s32) = G_AND [[COPY270]], [[C1]] ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C1]]
; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND134]], [[C16]](s32) ; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C22]](s32)
; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]] ; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
; CHECK: [[COPY271:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32) ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND135:%[0-9]+]]:_(s32) = G_AND [[COPY271]], [[C1]] ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C1]]
; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND135]], [[C17]](s32) ; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C23]](s32)
; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]] ; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
; CHECK: [[COPY272:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND136:%[0-9]+]]:_(s32) = G_AND [[COPY272]], [[C1]] ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C1]]
; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND136]], [[C4]](s32) ; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C24]](s32)
; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]] ; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CHECK: [[COPY273:%[0-9]+]]:_(s32) = COPY [[UV17]](s32) ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND137:%[0-9]+]]:_(s32) = G_AND [[COPY273]], [[C1]] ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C1]]
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 ; CHECK: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND137]], [[C18]](s32) ; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C25]](s32)
; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]] ; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
; CHECK: [[COPY274:%[0-9]+]]:_(s32) = COPY [[LSHR32]](s32) ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND138:%[0-9]+]]:_(s32) = G_AND [[COPY274]], [[C1]] ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C1]]
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 18 ; CHECK: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND138]], [[C19]](s32) ; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C26]](s32)
; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]] ; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
; CHECK: [[COPY275:%[0-9]+]]:_(s32) = COPY [[LSHR33]](s32) ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND139:%[0-9]+]]:_(s32) = G_AND [[COPY275]], [[C1]] ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C1]]
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 19 ; CHECK: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND139]], [[C20]](s32) ; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C27]](s32)
; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]] ; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
; CHECK: [[COPY276:%[0-9]+]]:_(s32) = COPY [[LSHR34]](s32) ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND140:%[0-9]+]]:_(s32) = G_AND [[COPY276]], [[C1]] ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C1]]
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 ; CHECK: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND140]], [[C21]](s32) ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C28]](s32)
; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]] ; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; CHECK: [[COPY277:%[0-9]+]]:_(s32) = COPY [[LSHR35]](s32) ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND141:%[0-9]+]]:_(s32) = G_AND [[COPY277]], [[C1]] ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C1]]
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 21 ; CHECK: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND141]], [[C22]](s32) ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C29]](s32)
; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]] ; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
; CHECK: [[COPY278:%[0-9]+]]:_(s32) = COPY [[LSHR36]](s32) ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND142:%[0-9]+]]:_(s32) = G_AND [[COPY278]], [[C1]] ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C1]]
; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 22 ; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND142]], [[C23]](s32) ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C30]](s32)
; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]] ; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
; CHECK: [[COPY279:%[0-9]+]]:_(s32) = COPY [[LSHR37]](s32) ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND143:%[0-9]+]]:_(s32) = G_AND [[COPY279]], [[C1]] ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C1]]
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 23 ; CHECK: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND143]], [[C24]](s32) ; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C31]](s32)
; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]] ; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
; CHECK: [[COPY280:%[0-9]+]]:_(s32) = COPY [[LSHR38]](s32) ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND144:%[0-9]+]]:_(s32) = G_AND [[COPY280]], [[C1]] ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C1]]
; CHECK: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND144]], [[C25]](s32) ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C1]]
; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]] ; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND33]], [[C1]](s32)
; CHECK: [[COPY281:%[0-9]+]]:_(s32) = COPY [[LSHR39]](s32) ; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[AND32]], [[SHL31]]
; CHECK: [[AND145:%[0-9]+]]:_(s32) = G_AND [[COPY281]], [[C1]] ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C1]]
; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND145]], [[C26]](s32) ; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C2]](s32)
; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]] ; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
; CHECK: [[COPY282:%[0-9]+]]:_(s32) = COPY [[LSHR40]](s32) ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND146:%[0-9]+]]:_(s32) = G_AND [[COPY282]], [[C1]] ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C1]]
; CHECK: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 26 ; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C3]](s32)
; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND146]], [[C27]](s32)
; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]] ; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
; CHECK: [[COPY283:%[0-9]+]]:_(s32) = COPY [[LSHR41]](s32) ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND147:%[0-9]+]]:_(s32) = G_AND [[COPY283]], [[C1]] ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[C1]]
; CHECK: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 27 ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C4]](s32)
; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND147]], [[C28]](s32)
; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]] ; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
; CHECK: [[COPY284:%[0-9]+]]:_(s32) = COPY [[LSHR42]](s32) ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND148:%[0-9]+]]:_(s32) = G_AND [[COPY284]], [[C1]] ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C1]]
; CHECK: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 28 ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C5]](s32)
; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND148]], [[C29]](s32)
; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[OR34]], [[SHL35]] ; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[OR34]], [[SHL35]]
; CHECK: [[COPY285:%[0-9]+]]:_(s32) = COPY [[LSHR43]](s32) ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND149:%[0-9]+]]:_(s32) = G_AND [[COPY285]], [[C1]] ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C1]]
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 29 ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C6]](s32)
; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND149]], [[C30]](s32)
; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]] ; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
; CHECK: [[COPY286:%[0-9]+]]:_(s32) = COPY [[LSHR44]](s32) ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND150:%[0-9]+]]:_(s32) = G_AND [[COPY286]], [[C1]] ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C1]]
; CHECK: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 30 ; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C7]](s32)
; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND150]], [[C31]](s32)
; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]] ; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
; CHECK: [[COPY287:%[0-9]+]]:_(s32) = COPY [[LSHR45]](s32) ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND151:%[0-9]+]]:_(s32) = G_AND [[COPY287]], [[C1]] ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C1]]
; CHECK: [[C32:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C8]](s32)
; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND151]], [[C32]](s32)
; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]] ; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
; CHECK: [[COPY288:%[0-9]+]]:_(s32) = COPY [[LSHR46]](s32) ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND152:%[0-9]+]]:_(s32) = G_AND [[COPY288]], [[C1]] ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C1]]
; CHECK: [[COPY289:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32) ; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[C9]](s32)
; CHECK: [[AND153:%[0-9]+]]:_(s32) = G_AND [[COPY289]], [[C1]] ; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND153]], [[C1]](s32) ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[AND152]], [[SHL39]] ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY42]], [[C1]]
; CHECK: [[COPY290:%[0-9]+]]:_(s32) = COPY [[UV34]](s32) ; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C10]](s32)
; CHECK: [[AND154:%[0-9]+]]:_(s32) = G_AND [[COPY290]], [[C1]]
; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND154]], [[C2]](s32)
; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]] ; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
; CHECK: [[COPY291:%[0-9]+]]:_(s32) = COPY [[LSHR63]](s32) ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND155:%[0-9]+]]:_(s32) = G_AND [[COPY291]], [[C1]] ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C1]]
; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND155]], [[C3]](s32) ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C11]](s32)
; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]] ; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
; CHECK: [[COPY292:%[0-9]+]]:_(s32) = COPY [[LSHR64]](s32) ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND156:%[0-9]+]]:_(s32) = G_AND [[COPY292]], [[C1]] ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY44]], [[C1]]
; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND156]], [[C6]](s32) ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C12]](s32)
; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[OR41]], [[SHL42]] ; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[OR41]], [[SHL42]]
; CHECK: [[COPY293:%[0-9]+]]:_(s32) = COPY [[LSHR65]](s32) ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND157:%[0-9]+]]:_(s32) = G_AND [[COPY293]], [[C1]] ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C1]]
; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND157]], [[C7]](s32) ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C13]](s32)
; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]] ; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
; CHECK: [[COPY294:%[0-9]+]]:_(s32) = COPY [[LSHR66]](s32) ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND158:%[0-9]+]]:_(s32) = G_AND [[COPY294]], [[C1]] ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY46]], [[C1]]
; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND158]], [[C8]](s32) ; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C14]](s32)
; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]] ; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
; CHECK: [[COPY295:%[0-9]+]]:_(s32) = COPY [[LSHR67]](s32) ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND159:%[0-9]+]]:_(s32) = G_AND [[COPY295]], [[C1]] ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C1]]
; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND159]], [[C9]](s32) ; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C15]](s32)
; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]] ; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
; CHECK: [[COPY296:%[0-9]+]]:_(s32) = COPY [[LSHR68]](s32) ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND160:%[0-9]+]]:_(s32) = G_AND [[COPY296]], [[C1]] ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY48]], [[C1]]
; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND160]], [[C10]](s32) ; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C16]](s32)
; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]] ; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
; CHECK: [[COPY297:%[0-9]+]]:_(s32) = COPY [[LSHR69]](s32) ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND161:%[0-9]+]]:_(s32) = G_AND [[COPY297]], [[C1]] ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C1]]
; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND161]], [[C11]](s32) ; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND49]], [[C17]](s32)
; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]] ; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
; CHECK: [[COPY298:%[0-9]+]]:_(s32) = COPY [[LSHR70]](s32) ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND162:%[0-9]+]]:_(s32) = G_AND [[COPY298]], [[C1]] ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY50]], [[C1]]
; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND162]], [[C12]](s32) ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C18]](s32)
; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]] ; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
; CHECK: [[COPY299:%[0-9]+]]:_(s32) = COPY [[LSHR71]](s32) ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND163:%[0-9]+]]:_(s32) = G_AND [[COPY299]], [[C1]] ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C1]]
; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND163]], [[C13]](s32) ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C19]](s32)
; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[OR48]], [[SHL49]] ; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[OR48]], [[SHL49]]
; CHECK: [[COPY300:%[0-9]+]]:_(s32) = COPY [[LSHR72]](s32) ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND164:%[0-9]+]]:_(s32) = G_AND [[COPY300]], [[C1]] ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY52]], [[C1]]
; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND164]], [[C14]](s32) ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C20]](s32)
; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]] ; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
; CHECK: [[COPY301:%[0-9]+]]:_(s32) = COPY [[LSHR73]](s32) ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND165:%[0-9]+]]:_(s32) = G_AND [[COPY301]], [[C1]] ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C1]]
; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND165]], [[C15]](s32) ; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C21]](s32)
; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]] ; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
; CHECK: [[COPY302:%[0-9]+]]:_(s32) = COPY [[LSHR74]](s32) ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND166:%[0-9]+]]:_(s32) = G_AND [[COPY302]], [[C1]] ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C1]]
; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND166]], [[C16]](s32) ; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C22]](s32)
; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]] ; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
; CHECK: [[COPY303:%[0-9]+]]:_(s32) = COPY [[LSHR75]](s32) ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND167:%[0-9]+]]:_(s32) = G_AND [[COPY303]], [[C1]] ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C1]]
; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND167]], [[C17]](s32) ; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C23]](s32)
; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]] ; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
; CHECK: [[COPY304:%[0-9]+]]:_(s32) = COPY [[LSHR76]](s32) ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND168:%[0-9]+]]:_(s32) = G_AND [[COPY304]], [[C1]] ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY56]], [[C1]]
; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND168]], [[C4]](s32) ; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C24]](s32)
; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]] ; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
; CHECK: [[COPY305:%[0-9]+]]:_(s32) = COPY [[LSHR77]](s32) ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND169:%[0-9]+]]:_(s32) = G_AND [[COPY305]], [[C1]] ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C1]]
; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND169]], [[C18]](s32) ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND57]], [[C25]](s32)
; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]] ; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
; CHECK: [[COPY306:%[0-9]+]]:_(s32) = COPY [[LSHR62]](s32) ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND170:%[0-9]+]]:_(s32) = G_AND [[COPY306]], [[C1]] ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY58]], [[C1]]
; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[AND170]], [[C19]](s32) ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C26]](s32)
; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[OR55]], [[SHL56]] ; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[OR55]], [[SHL56]]
; CHECK: [[COPY307:%[0-9]+]]:_(s32) = COPY [[UV51]](s32) ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND171:%[0-9]+]]:_(s32) = G_AND [[COPY307]], [[C1]] ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C1]]
; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[AND171]], [[C20]](s32) ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C27]](s32)
; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]] ; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
; CHECK: [[COPY308:%[0-9]+]]:_(s32) = COPY [[LSHR94]](s32) ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND172:%[0-9]+]]:_(s32) = G_AND [[COPY308]], [[C1]] ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C1]]
; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[AND172]], [[C21]](s32) ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C28]](s32)
; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]] ; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
; CHECK: [[COPY309:%[0-9]+]]:_(s32) = COPY [[LSHR95]](s32) ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND173:%[0-9]+]]:_(s32) = G_AND [[COPY309]], [[C1]] ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C1]]
; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[AND173]], [[C22]](s32) ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C29]](s32)
; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]] ; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
; CHECK: [[COPY310:%[0-9]+]]:_(s32) = COPY [[LSHR96]](s32) ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND174:%[0-9]+]]:_(s32) = G_AND [[COPY310]], [[C1]] ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C1]]
; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[AND174]], [[C23]](s32) ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C30]](s32)
; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]] ; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
; CHECK: [[COPY311:%[0-9]+]]:_(s32) = COPY [[LSHR97]](s32) ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND175:%[0-9]+]]:_(s32) = G_AND [[COPY311]], [[C1]] ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C1]]
; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[AND175]], [[C24]](s32) ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C31]](s32)
; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]] ; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
; CHECK: [[COPY312:%[0-9]+]]:_(s32) = COPY [[LSHR98]](s32) ; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND176:%[0-9]+]]:_(s32) = G_AND [[COPY312]], [[C1]] ; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[COPY64]], [[C1]]
; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[AND176]], [[C25]](s32) ; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[OR61]], [[SHL62]] ; CHECK: [[AND65:%[0-9]+]]:_(s32) = G_AND [[COPY65]], [[C1]]
; CHECK: [[COPY313:%[0-9]+]]:_(s32) = COPY [[LSHR99]](s32) ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[AND65]], [[C1]](s32)
; CHECK: [[AND177:%[0-9]+]]:_(s32) = G_AND [[COPY313]], [[C1]] ; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL62]]
; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[AND177]], [[C26]](s32) ; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND66:%[0-9]+]]:_(s32) = G_AND [[COPY66]], [[C1]]
; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[AND66]], [[C2]](s32)
; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[OR62]], [[SHL63]] ; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[OR62]], [[SHL63]]
; CHECK: [[COPY314:%[0-9]+]]:_(s32) = COPY [[LSHR100]](s32) ; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND178:%[0-9]+]]:_(s32) = G_AND [[COPY314]], [[C1]] ; CHECK: [[AND67:%[0-9]+]]:_(s32) = G_AND [[COPY67]], [[C1]]
; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[AND178]], [[C27]](s32) ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[AND67]], [[C3]](s32)
; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]] ; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
; CHECK: [[COPY315:%[0-9]+]]:_(s32) = COPY [[LSHR101]](s32) ; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND179:%[0-9]+]]:_(s32) = G_AND [[COPY315]], [[C1]] ; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY68]], [[C4]](s32)
; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[AND179]], [[C28]](s32)
; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]] ; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
; CHECK: [[COPY316:%[0-9]+]]:_(s32) = COPY [[LSHR102]](s32) ; CHECK: [[COPY69:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND180:%[0-9]+]]:_(s32) = G_AND [[COPY316]], [[C1]] ; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY69]], [[C5]](s32)
; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[AND180]], [[C29]](s32)
; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]] ; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
; CHECK: [[COPY317:%[0-9]+]]:_(s32) = COPY [[LSHR103]](s32) ; CHECK: [[COPY70:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND181:%[0-9]+]]:_(s32) = G_AND [[COPY317]], [[C1]] ; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY70]], [[C6]](s32)
; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[AND181]], [[C30]](s32)
; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]] ; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
; CHECK: [[COPY318:%[0-9]+]]:_(s32) = COPY [[LSHR104]](s32) ; CHECK: [[COPY71:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND182:%[0-9]+]]:_(s32) = G_AND [[COPY318]], [[C1]] ; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY71]], [[C7]](s32)
; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[AND182]], [[C31]](s32)
; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]] ; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
; CHECK: [[COPY319:%[0-9]+]]:_(s32) = COPY [[LSHR105]](s32) ; CHECK: [[COPY72:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND183:%[0-9]+]]:_(s32) = G_AND [[COPY319]], [[C1]] ; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY72]], [[C8]](s32)
; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[AND183]], [[C32]](s32)
; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]] ; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
; CHECK: [[COPY320:%[0-9]+]]:_(s32) = COPY [[LSHR106]](s32) ; CHECK: [[COPY73:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND184:%[0-9]+]]:_(s32) = G_AND [[COPY320]], [[C1]] ; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY73]], [[C9]](s32)
; CHECK: [[COPY321:%[0-9]+]]:_(s32) = COPY [[LSHR107]](s32) ; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[OR69]], [[SHL70]]
; CHECK: [[AND185:%[0-9]+]]:_(s32) = G_AND [[COPY321]], [[C1]] ; CHECK: [[COPY74:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[AND185]], [[C1]](s32) ; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY74]], [[C10]](s32)
; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[AND184]], [[SHL70]]
; CHECK: [[COPY322:%[0-9]+]]:_(s32) = COPY [[LSHR108]](s32)
; CHECK: [[AND186:%[0-9]+]]:_(s32) = G_AND [[COPY322]], [[C1]]
; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[AND186]], [[C2]](s32)
; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]] ; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
; CHECK: [[COPY323:%[0-9]+]]:_(s32) = COPY [[LSHR93]](s32) ; CHECK: [[COPY75:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND187:%[0-9]+]]:_(s32) = G_AND [[COPY323]], [[C1]] ; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY75]], [[C11]](s32)
; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[AND187]], [[C3]](s32)
; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]] ; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
; CHECK: [[COPY324:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY76:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY324]], [[C6]](s32) ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY76]], [[C12]](s32)
; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]] ; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
; CHECK: [[COPY325:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY77:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY325]], [[C7]](s32) ; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY77]], [[C13]](s32)
; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]] ; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
; CHECK: [[COPY326:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY78:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY326]], [[C8]](s32) ; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY78]], [[C14]](s32)
; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]] ; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
; CHECK: [[COPY327:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY79:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY327]], [[C9]](s32) ; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY79]], [[C15]](s32)
; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]] ; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
; CHECK: [[COPY328:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY328]], [[C10]](s32) ; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY80]], [[C16]](s32)
; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[OR76]], [[SHL77]] ; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[OR76]], [[SHL77]]
; CHECK: [[COPY329:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY329]], [[C11]](s32) ; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY81]], [[C17]](s32)
; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]] ; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
; CHECK: [[COPY330:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY330]], [[C12]](s32) ; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY82]], [[C18]](s32)
; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]] ; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
; CHECK: [[COPY331:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY331]], [[C13]](s32) ; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY83]], [[C19]](s32)
; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]] ; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
; CHECK: [[COPY332:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY332]], [[C14]](s32) ; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY84]], [[C20]](s32)
; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]] ; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
; CHECK: [[COPY333:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY333]], [[C15]](s32) ; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY85]], [[C21]](s32)
; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]] ; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
; CHECK: [[COPY334:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY334]], [[C16]](s32) ; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY86]], [[C22]](s32)
; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]] ; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
; CHECK: [[COPY335:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY335]], [[C17]](s32) ; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY87]], [[C23]](s32)
; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[OR83]], [[SHL84]] ; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[OR83]], [[SHL84]]
; CHECK: [[COPY336:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY336]], [[C4]](s32) ; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY88]], [[C24]](s32)
; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]] ; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
; CHECK: [[COPY337:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY89:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY337]], [[C18]](s32) ; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY89]], [[C25]](s32)
; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]] ; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
; CHECK: [[COPY338:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY90:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY338]], [[C19]](s32) ; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY90]], [[C26]](s32)
; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]] ; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
; CHECK: [[COPY339:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY91:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY339]], [[C20]](s32) ; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY91]], [[C27]](s32)
; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]] ; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
; CHECK: [[COPY340:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY92:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY340]], [[C21]](s32) ; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY92]], [[C28]](s32)
; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]] ; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
; CHECK: [[COPY341:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY93:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY341]], [[C22]](s32) ; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY93]], [[C29]](s32)
; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]] ; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
; CHECK: [[COPY342:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY94:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY342]], [[C23]](s32) ; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY94]], [[C30]](s32)
; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[OR90]], [[SHL91]] ; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[OR90]], [[SHL91]]
; CHECK: [[COPY343:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[COPY95:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY343]], [[C24]](s32) ; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY95]], [[C31]](s32)
; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]] ; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
; CHECK: [[COPY344:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR30]](s32), [[OR61]](s32), [[OR92]](s32)
; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY344]], [[C25]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s68) = G_TRUNC [[MV]](s96)
; CHECK: [[OR93:%[0-9]+]]:_(s32) = G_OR [[OR92]], [[SHL93]] ; CHECK: S_NOP 0, implicit [[TRUNC]](s68)
; CHECK: [[COPY345:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY345]], [[C26]](s32)
; CHECK: [[OR94:%[0-9]+]]:_(s32) = G_OR [[OR93]], [[SHL94]]
; CHECK: [[COPY346:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY346]], [[C27]](s32)
; CHECK: [[OR95:%[0-9]+]]:_(s32) = G_OR [[OR94]], [[SHL95]]
; CHECK: [[COPY347:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY347]], [[C28]](s32)
; CHECK: [[OR96:%[0-9]+]]:_(s32) = G_OR [[OR95]], [[SHL96]]
; CHECK: [[COPY348:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY348]], [[C29]](s32)
; CHECK: [[OR97:%[0-9]+]]:_(s32) = G_OR [[OR96]], [[SHL97]]
; CHECK: [[COPY349:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY349]], [[C30]](s32)
; CHECK: [[OR98:%[0-9]+]]:_(s32) = G_OR [[OR97]], [[SHL98]]
; CHECK: [[COPY350:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY350]], [[C31]](s32)
; CHECK: [[OR99:%[0-9]+]]:_(s32) = G_OR [[OR98]], [[SHL99]]
; CHECK: [[COPY351:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY351]], [[C32]](s32)
; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[OR99]], [[SHL100]]
; CHECK: [[MV8:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR38]](s32), [[OR69]](s32), [[OR100]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s68) = G_TRUNC [[MV8]](s96)
; CHECK: S_NOP 0, implicit [[TRUNC4]](s68)
%0:_(s17) = G_CONSTANT i17 0 %0:_(s17) = G_CONSTANT i17 0
%1:_(s17) = G_CONSTANT i17 1 %1:_(s17) = G_CONSTANT i17 1
%2:_(s17) = G_CONSTANT i17 2 %2:_(s17) = G_CONSTANT i17 2
%3:_(s17) = G_CONSTANT i17 3 %3:_(s17) = G_CONSTANT i17 3
%4:_(s68) = G_MERGE_VALUES %0, %1, %2, %3 %4:_(s68) = G_MERGE_VALUES %0, %1, %2, %3
S_NOP 0, implicit %4 S_NOP 0, implicit %4
... ...
--- ---
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2 liveins: $vgpr0_vgpr1, $vgpr2
; SI-LABEL: name: test_store_global_s16_align1 ; SI-LABEL: name: test_store_global_s16_align1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) ; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store 1, addrspace 1) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store 1 + 1, addrspace 1)
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store 1 + 1, addrspace 1)
; CI-LABEL: name: test_store_global_s16_align1 ; CI-LABEL: name: test_store_global_s16_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 2, align 1, addrspace 1) ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 2, align 1, addrspace 1)
; VI-LABEL: name: test_store_global_s16_align1 ; VI-LABEL: name: test_store_global_s16_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C]](s16) ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 1, addrspace 1) ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64) ; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store 1 + 1, addrspace 1) ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store 1 + 1, addrspace 1)
; GFX9-LABEL: name: test_store_global_s16_align1 ; GFX9-LABEL: name: test_store_global_s16_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 2, align 1, addrspace 1) ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store 2, align 1, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2 %1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
▲ Show 20 Lines • Show All 8,332 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
name: test_unmerge_s8_s16 name: test_unmerge_s8_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_s16 ; CHECK-LABEL: name: test_unmerge_s8_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr1 = COPY [[COPY3]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s8), %3:_(s8) = G_UNMERGE_VALUES %1 %2:_(s8), %3:_(s8) = G_UNMERGE_VALUES %1
%4:_(s32) = G_ANYEXT %2 %4:_(s32) = G_ANYEXT %2
%5:_(s32) = G_ANYEXT %3 %5:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
$vgpr1 = COPY %5 $vgpr1 = COPY %5
... ...
Show All 34 Lines
--- ---
name: test_unmerge_s8_s48 name: test_unmerge_s8_s48
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s8_s48 ; CHECK-LABEL: name: test_unmerge_s8_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32) ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C1]](s32) ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV2]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV3]](s32) ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32) ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: $vgpr0 = COPY [[COPY6]](s32) ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
; CHECK: $vgpr1 = COPY [[COPY7]](s32) ; CHECK: $vgpr1 = COPY [[COPY7]](s32)
; CHECK: $vgpr2 = COPY [[COPY8]](s32) ; CHECK: $vgpr2 = COPY [[COPY8]](s32)
; CHECK: $vgpr3 = COPY [[COPY9]](s32) ; CHECK: $vgpr3 = COPY [[COPY9]](s32)
; CHECK: $vgpr4 = COPY [[COPY10]](s32) ; CHECK: $vgpr4 = COPY [[COPY10]](s32)
; CHECK: $vgpr5 = COPY [[COPY11]](s32) ; CHECK: $vgpr5 = COPY [[COPY11]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
Show All 16 Lines
--- ---
name: test_unmerge_s16_s48 name: test_unmerge_s16_s48
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_unmerge_s16_s48 ; CHECK-LABEL: name: test_unmerge_s16_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV2]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV3]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: $vgpr1 = COPY [[COPY2]](s32) ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: $vgpr2 = COPY [[COPY3]](s32) ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0 %1:_(s48) = G_TRUNC %0
%2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %1 %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %1
%5:_(s32) = G_ANYEXT %2 %5:_(s32) = G_ANYEXT %2
%6:_(s32) = G_ANYEXT %3 %6:_(s32) = G_ANYEXT %3
▲ Show 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
--- ---
name: test_unmerge_s1_s3 name: test_unmerge_s1_s3
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s1_s3 ; CHECK-LABEL: name: test_unmerge_s1_s3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C4]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C6]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C7]](s32)
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C8]](s32)
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C9]](s32)
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C10]](s32)
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C11]](s32)
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C12]](s32)
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C13]](s32)
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C14]](s32)
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C15]](s32)
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C16]](s32)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
; CHECK: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C17]](s32)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C18]](s32)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C19]](s32)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
; CHECK: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C20]](s32)
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
; CHECK: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C21]](s32)
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; CHECK: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C22]](s32)
; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C23]](s32)
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C24]](s32)
; CHECK: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; CHECK: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C25]](s32)
; CHECK: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
; CHECK: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C26]](s32)
; CHECK: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C27]](s32)
; CHECK: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; CHECK: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C28]](s32)
; CHECK: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C29]](s32)
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C30]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32)
; CHECK: $vgpr1 = COPY [[COPY4]](s32)
; CHECK: $vgpr2 = COPY [[COPY5]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s3) = G_TRUNC %0 %1:_(s3) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1) = G_UNMERGE_VALUES %1 %2:_(s1), %3:_(s1), %4:_(s1) = G_UNMERGE_VALUES %1
%5:_(s32) = G_ANYEXT %2 %5:_(s32) = G_ANYEXT %2
%6:_(s32) = G_ANYEXT %3 %6:_(s32) = G_ANYEXT %3
%7:_(s32) = G_ANYEXT %4 %7:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
$vgpr1 = COPY %6 $vgpr1 = COPY %6
$vgpr2 = COPY %7 $vgpr2 = COPY %7
... ...
--- ---
name: test_unmerge_s1_s8 name: test_unmerge_s1_s8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s1_s8 ; CHECK-LABEL: name: test_unmerge_s1_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C4]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C6]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C7]](s32)
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C8]](s32)
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C9]](s32)
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C10]](s32)
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C11]](s32)
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C12]](s32)
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C13]](s32)
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C14]](s32)
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C15]](s32)
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C16]](s32)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
; CHECK: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C17]](s32)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C18]](s32)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C19]](s32)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
; CHECK: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C20]](s32)
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
; CHECK: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C21]](s32)
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; CHECK: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C22]](s32)
; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C23]](s32)
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C24]](s32)
; CHECK: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; CHECK: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C25]](s32)
; CHECK: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
; CHECK: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C26]](s32)
; CHECK: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C27]](s32)
; CHECK: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; CHECK: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C28]](s32)
; CHECK: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C29]](s32)
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C30]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32) ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr4 = COPY [[COPY5]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; CHECK: $vgpr5 = COPY [[COPY6]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32) ; CHECK: $vgpr6 = COPY [[COPY7]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: $vgpr7 = COPY [[COPY8]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C6]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: $vgpr0 = COPY [[COPY8]](s32)
; CHECK: $vgpr1 = COPY [[COPY9]](s32)
; CHECK: $vgpr2 = COPY [[COPY10]](s32)
; CHECK: $vgpr3 = COPY [[COPY11]](s32)
; CHECK: $vgpr4 = COPY [[COPY12]](s32)
; CHECK: $vgpr5 = COPY [[COPY13]](s32)
; CHECK: $vgpr6 = COPY [[COPY14]](s32)
; CHECK: $vgpr7 = COPY [[COPY15]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1), %5:_(s1), %6:_(s1), %7:_(s1), %8:_(s1), %9:_(s1) = G_UNMERGE_VALUES %1 %2:_(s1), %3:_(s1), %4:_(s1), %5:_(s1), %6:_(s1), %7:_(s1), %8:_(s1), %9:_(s1) = G_UNMERGE_VALUES %1
%10:_(s32) = G_ANYEXT %2 %10:_(s32) = G_ANYEXT %2
%11:_(s32) = G_ANYEXT %3 %11:_(s32) = G_ANYEXT %3
%12:_(s32) = G_ANYEXT %4 %12:_(s32) = G_ANYEXT %4
%13:_(s32) = G_ANYEXT %5 %13:_(s32) = G_ANYEXT %5
%14:_(s32) = G_ANYEXT %6 %14:_(s32) = G_ANYEXT %6
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
--- ---
name: test_unmerge_s8_v3s8 name: test_unmerge_s8_v3s8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v3s8 ; CHECK-LABEL: name: test_unmerge_s8_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[MV1:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64) ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV1]](s192) ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[TRUNC]](s96) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32)
; CHECK: $vgpr1 = COPY [[COPY5]](s32)
; CHECK: $vgpr2 = COPY [[COPY6]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0 %1:_(s24) = G_TRUNC %0
%2:_(<3 x s8>) = G_BITCAST %1 %2:_(<3 x s8>) = G_BITCAST %1
%3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %2 %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %2
%6:_(s32) = G_ANYEXT %3 %6:_(s32) = G_ANYEXT %3
%7:_(s32) = G_ANYEXT %4 %7:_(s32) = G_ANYEXT %4
%8:_(s32) = G_ANYEXT %5 %8:_(s32) = G_ANYEXT %5
$vgpr0 = COPY %6 $vgpr0 = COPY %6
$vgpr1 = COPY %7 $vgpr1 = COPY %7
$vgpr2 = COPY %8 $vgpr2 = COPY %8
... ...
--- ---
name: test_unmerge_s8_v2s8 name: test_unmerge_s8_v2s8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_unmerge_s8_v2s8 ; CHECK-LABEL: name: test_unmerge_s8_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32) ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: $vgpr0 = COPY [[COPY2]](s32)
; CHECK: $vgpr1 = COPY [[COPY3]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(<2 x s8>) = G_BITCAST %1 %2:_(<2 x s8>) = G_BITCAST %1
%3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %2 %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ANYEXT %3 %5:_(s32) = G_ANYEXT %3
%6:_(s32) = G_ANYEXT %4 %6:_(s32) = G_ANYEXT %4
$vgpr0 = COPY %5 $vgpr0 = COPY %5
$vgpr1 = COPY %6 $vgpr1 = COPY %6
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines; GFX6-NEXT: s_setpc_b64 s[30:31]
%ext = zext i32 %load to i64 %ext = zext i32 %load to i64
ret i64 %ext ret i64 %ext
} }
define i96 @zextload_global_i32_to_i96(i32 addrspace(1)* %ptr) { define i96 @zextload_global_i32_to_i96(i32 addrspace(1)* %ptr) {
; GFX9-LABEL: zextload_global_i32_to_i96: ; GFX9-LABEL: zextload_global_i32_to_i96:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v3, v1 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v2, v0 ; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: global_load_dword v0, v[2:3], off
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: zextload_global_i32_to_i96: ; GFX8-LABEL: zextload_global_i32_to_i96:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v3, v1 ; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v2, v0 ; GFX8-NEXT: s_mov_b32 s4, 0
; GFX8-NEXT: flat_load_dword v0, v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v3, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX6-LABEL: zextload_global_i32_to_i96: ; GFX6-LABEL: zextload_global_i32_to_i96:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v3, v1
; GFX6-NEXT: v_mov_b32_e32 v2, v0
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[4:5], 0 ; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_dword v0, v[2:3], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-NEXT: v_mov_b32_e32 v2, 0 ; GFX6-NEXT: s_mov_b32 s8, 0
; GFX6-NEXT: v_mov_b32_e32 v1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_mov_b32_e32 v3, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
%load = load i32, i32 addrspace(1)* %ptr %load = load i32, i32 addrspace(1)* %ptr
%ext = zext i32 %load to i96 %ext = zext i32 %load to i96
ret i96 %ext ret i96 %ext
} }
define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) { define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) {
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines