[RISCV] Support Constant Pools in Load/Store Peephole

[lenary]

Summary

RISC-V uses a post-select peephole pass to optimise
(load/store (ADDI $reg, %lo(addr)), 0) into (load/store $reg, %lo(addr)).
This peephole wasn't firing for accesses to constant pools, which is how we
materialise most floating point constants.

This adds support for the constantpool case, which improves code generation for
lots of small FP loading examples. I have not added any tests because this
structure is well-covered by the fp-imm.ll testcases, as well as almost
all other uses of floating point constants in the RISC-V backend tests.

[luismarques]

LGTM. Nice to see this extraneous addi go!

[asb]

LGTM, thanks. Left an inline comment pointing out a TODO that can now be removed thanks to this.

llvm/test/CodeGen/RISCV/float-imm.ll

24–25

This TODO can be deleted thanks to this patch!

[lenary]

• Remove TODO which is now done!

[lenary]

• I missed a test on a previous update.

[lenary]

I had to back this out in rG3242e5653a5 due to an API update which caused my build to fail. Will re-land soon.

[lenary]

• getAlign API Update

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

while (Position != CurDAG->allnodes_begin()) {
 
     if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) {
       ImmOperand = CurDAG->getTargetConstant(
           Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType());
     } else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
       ImmOperand = CurDAG->getTargetGlobalAddress(
           GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
           GA->getOffset(), GA->getTargetFlags());
+    } else if (auto CP = dyn_cast<ConstantPoolSDNode>(ImmOperand)) {
+      ImmOperand = CurDAG->getTargetConstantPool(
+          CP->getConstVal(), ImmOperand.getValueType(), CP->getAlign(),
+          CP->getOffset(), CP->getTargetFlags());
     } else {
       continue;
     }
 
     LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase:    ");
     LLVM_DEBUG(Base->dump(CurDAG));
     LLVM_DEBUG(dbgs() << "\nN: ");
     LLVM_DEBUG(N->dump(CurDAG));

llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

 }
 
 define i32 @caller_double_in_fpr() nounwind {
 ; RV32-ILP32D-LABEL: caller_double_in_fpr:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI1_0)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    call callee_double_in_fpr
 ; RV32-ILP32D-NEXT:    lw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    addi sp, sp, 16
 ; RV32-ILP32D-NEXT:    ret
   %1 = call i32 @callee_double_in_fpr(i32 1, double 2.0)
   ret i32 %1
 }

 
 define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
 ; RV32-ILP32D-LABEL: caller_double_in_fpr_exhausted_gprs:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    addi a1, zero, 5
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    addi a2, zero, 2
 ; RV32-ILP32D-NEXT:    addi a4, zero, 3
 ; RV32-ILP32D-NEXT:    addi a6, zero, 4
 ; RV32-ILP32D-NEXT:    sw a1, 0(sp)
 ; RV32-ILP32D-NEXT:    mv a1, zero
 ; RV32-ILP32D-NEXT:    mv a3, zero
 ; RV32-ILP32D-NEXT:    mv a5, zero

 }
 
 define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
 ; RV32-ILP32D-LABEL: caller_double_in_gpr_exhausted_fprs:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI5_0)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_1)
-; RV32-ILP32D-NEXT:    fld fa1, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa1, %lo(.LCPI5_1)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_2)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_2)
-; RV32-ILP32D-NEXT:    fld fa2, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa2, %lo(.LCPI5_2)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_3)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_3)
-; RV32-ILP32D-NEXT:    fld fa3, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa3, %lo(.LCPI5_3)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_4)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_4)
-; RV32-ILP32D-NEXT:    fld fa4, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa4, %lo(.LCPI5_4)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_5)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_5)
-; RV32-ILP32D-NEXT:    fld fa5, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa5, %lo(.LCPI5_5)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_6)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_6)
-; RV32-ILP32D-NEXT:    fld fa6, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa6, %lo(.LCPI5_6)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI5_7)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI5_7)
-; RV32-ILP32D-NEXT:    fld fa7, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa7, %lo(.LCPI5_7)(a0)
 ; RV32-ILP32D-NEXT:    lui a1, 262688
 ; RV32-ILP32D-NEXT:    mv a0, zero
 ; RV32-ILP32D-NEXT:    call callee_double_in_gpr_exhausted_fprs
 ; RV32-ILP32D-NEXT:    lw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    addi sp, sp, 16
 ; RV32-ILP32D-NEXT:    ret
   %1 = call i32 @callee_double_in_gpr_exhausted_fprs(
       double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,

 
 define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind {
 ; RV32-ILP32D-LABEL: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a1, 262816
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI7_0)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_1)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_1)
-; RV32-ILP32D-NEXT:    fld fa1, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa1, %lo(.LCPI7_1)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_2)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_2)
-; RV32-ILP32D-NEXT:    fld fa2, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa2, %lo(.LCPI7_2)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_3)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_3)
-; RV32-ILP32D-NEXT:    fld fa3, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa3, %lo(.LCPI7_3)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_4)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_4)
-; RV32-ILP32D-NEXT:    fld fa4, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa4, %lo(.LCPI7_4)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_5)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_5)
-; RV32-ILP32D-NEXT:    fld fa5, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa5, %lo(.LCPI7_5)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_6)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_6)
-; RV32-ILP32D-NEXT:    fld fa6, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa6, %lo(.LCPI7_6)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI7_7)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI7_7)
-; RV32-ILP32D-NEXT:    fld fa7, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa7, %lo(.LCPI7_7)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    addi a2, zero, 3
 ; RV32-ILP32D-NEXT:    addi a4, zero, 5
 ; RV32-ILP32D-NEXT:    addi a6, zero, 7
 ; RV32-ILP32D-NEXT:    sw a1, 0(sp)
 ; RV32-ILP32D-NEXT:    mv a1, zero
 ; RV32-ILP32D-NEXT:    mv a3, zero
 ; RV32-ILP32D-NEXT:    mv a5, zero

 define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
 ; RV32-ILP32D-LABEL: caller_double_on_stack_exhausted_gprs_fprs:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16
 ; RV32-ILP32D-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    lui a0, 262816
 ; RV32-ILP32D-NEXT:    sw a0, 4(sp)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI9_0)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_1)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_1)
-; RV32-ILP32D-NEXT:    fld fa1, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa1, %lo(.LCPI9_1)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_2)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_2)
-; RV32-ILP32D-NEXT:    fld fa2, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa2, %lo(.LCPI9_2)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_3)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_3)
-; RV32-ILP32D-NEXT:    fld fa3, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa3, %lo(.LCPI9_3)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_4)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_4)
-; RV32-ILP32D-NEXT:    fld fa4, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa4, %lo(.LCPI9_4)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_5)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_5)
-; RV32-ILP32D-NEXT:    fld fa5, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa5, %lo(.LCPI9_5)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_6)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_6)
-; RV32-ILP32D-NEXT:    fld fa6, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa6, %lo(.LCPI9_6)(a0)
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI9_7)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI9_7)
-; RV32-ILP32D-NEXT:    fld fa7, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa7, %lo(.LCPI9_7)(a0)
 ; RV32-ILP32D-NEXT:    addi a0, zero, 1
 ; RV32-ILP32D-NEXT:    addi a2, zero, 3
 ; RV32-ILP32D-NEXT:    addi a4, zero, 5
 ; RV32-ILP32D-NEXT:    addi a6, zero, 7
 ; RV32-ILP32D-NEXT:    sw zero, 0(sp)
 ; RV32-ILP32D-NEXT:    mv a1, zero
 ; RV32-ILP32D-NEXT:    mv a3, zero
 ; RV32-ILP32D-NEXT:    mv a5, zero
 ; RV32-ILP32D-NEXT:    mv a7, zero
 ; RV32-ILP32D-NEXT:    call callee_double_on_stack_exhausted_gprs_fprs
 ; RV32-ILP32D-NEXT:    lw ra, 12(sp)
 ; RV32-ILP32D-NEXT:    addi sp, sp, 16
 ; RV32-ILP32D-NEXT:    ret
   %1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs(
       i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0,
       double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
   ret i32 %1
 }
 
 define double @callee_double_ret() nounwind {
 ; RV32-ILP32D-LABEL: callee_double_ret:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    lui a0, %hi(.LCPI10_0)
-; RV32-ILP32D-NEXT:    addi a0, a0, %lo(.LCPI10_0)
-; RV32-ILP32D-NEXT:    fld fa0, 0(a0)
+; RV32-ILP32D-NEXT:    fld fa0, %lo(.LCPI10_0)(a0)
 ; RV32-ILP32D-NEXT:    ret
   ret double 1.0
 }
 
 define i32 @caller_double_ret() nounwind {
 ; RV32-ILP32D-LABEL: caller_double_ret:
 ; RV32-ILP32D:       # %bb.0:
 ; RV32-ILP32D-NEXT:    addi sp, sp, -16

llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll

 }
 
 define i32 @caller_float_in_fpr() nounwind {
 ; RV32-ILP32FD-LABEL: caller_float_in_fpr:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV32-ILP32FD-NEXT:    addi a0, zero, 1
 ; RV32-ILP32FD-NEXT:    call callee_float_in_fpr
 ; RV32-ILP32FD-NEXT:    lw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    addi sp, sp, 16
 ; RV32-ILP32FD-NEXT:    ret
   %1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)
   ret i32 %1
 }

 
 define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
 ; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    addi a1, zero, 5
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
 ; RV32-ILP32FD-NEXT:    addi a0, zero, 1
 ; RV32-ILP32FD-NEXT:    addi a2, zero, 2
 ; RV32-ILP32FD-NEXT:    addi a4, zero, 3
 ; RV32-ILP32FD-NEXT:    addi a6, zero, 4
 ; RV32-ILP32FD-NEXT:    sw a1, 0(sp)
 ; RV32-ILP32FD-NEXT:    mv a1, zero
 ; RV32-ILP32FD-NEXT:    mv a3, zero
 ; RV32-ILP32FD-NEXT:    mv a5, zero

 }
 
 define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
 ; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI5_0)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_1)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_1)
-; RV32-ILP32FD-NEXT:    flw fa1, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa1, %lo(.LCPI5_1)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_2)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_2)
-; RV32-ILP32FD-NEXT:    flw fa2, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa2, %lo(.LCPI5_2)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_3)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_3)
-; RV32-ILP32FD-NEXT:    flw fa3, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa3, %lo(.LCPI5_3)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_4)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_4)
-; RV32-ILP32FD-NEXT:    flw fa4, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa4, %lo(.LCPI5_4)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_5)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_5)
-; RV32-ILP32FD-NEXT:    flw fa5, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa5, %lo(.LCPI5_5)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_6)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_6)
-; RV32-ILP32FD-NEXT:    flw fa6, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa6, %lo(.LCPI5_6)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI5_7)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI5_7)
-; RV32-ILP32FD-NEXT:    flw fa7, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa7, %lo(.LCPI5_7)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, 266496
 ; RV32-ILP32FD-NEXT:    call callee_float_in_gpr_exhausted_fprs
 ; RV32-ILP32FD-NEXT:    lw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    addi sp, sp, 16
 ; RV32-ILP32FD-NEXT:    ret
   %1 = call i32 @callee_float_in_gpr_exhausted_fprs(
       float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0,
       float 7.0, float 8.0, float 9.0)

 
 define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
 ; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16
 ; RV32-ILP32FD-NEXT:    sw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    lui a1, 267520
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI7_0)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_1)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_1)
-; RV32-ILP32FD-NEXT:    flw fa1, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa1, %lo(.LCPI7_1)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_2)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_2)
-; RV32-ILP32FD-NEXT:    flw fa2, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa2, %lo(.LCPI7_2)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_3)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_3)
-; RV32-ILP32FD-NEXT:    flw fa3, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa3, %lo(.LCPI7_3)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_4)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_4)
-; RV32-ILP32FD-NEXT:    flw fa4, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa4, %lo(.LCPI7_4)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_5)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_5)
-; RV32-ILP32FD-NEXT:    flw fa5, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa5, %lo(.LCPI7_5)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_6)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_6)
-; RV32-ILP32FD-NEXT:    flw fa6, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa6, %lo(.LCPI7_6)(a0)
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI7_7)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI7_7)
-; RV32-ILP32FD-NEXT:    flw fa7, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa7, %lo(.LCPI7_7)(a0)
 ; RV32-ILP32FD-NEXT:    addi a0, zero, 1
 ; RV32-ILP32FD-NEXT:    addi a2, zero, 3
 ; RV32-ILP32FD-NEXT:    addi a4, zero, 5
 ; RV32-ILP32FD-NEXT:    addi a6, zero, 7
 ; RV32-ILP32FD-NEXT:    sw a1, 0(sp)
 ; RV32-ILP32FD-NEXT:    mv a1, zero
 ; RV32-ILP32FD-NEXT:    mv a3, zero
 ; RV32-ILP32FD-NEXT:    mv a5, zero
 ; RV32-ILP32FD-NEXT:    mv a7, zero
 ; RV32-ILP32FD-NEXT:    call callee_float_on_stack_exhausted_gprs_fprs
 ; RV32-ILP32FD-NEXT:    lw ra, 12(sp)
 ; RV32-ILP32FD-NEXT:    addi sp, sp, 16
 ; RV32-ILP32FD-NEXT:    ret
   %1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(
       i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,
       float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)
   ret i32 %1
 }
 
 define float @callee_float_ret() nounwind {
 ; RV32-ILP32FD-LABEL: callee_float_ret:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    lui a0, %hi(.LCPI8_0)
-; RV32-ILP32FD-NEXT:    addi a0, a0, %lo(.LCPI8_0)
-; RV32-ILP32FD-NEXT:    flw fa0, 0(a0)
+; RV32-ILP32FD-NEXT:    flw fa0, %lo(.LCPI8_0)(a0)
 ; RV32-ILP32FD-NEXT:    ret
   ret float 1.0
 }
 
 define i32 @caller_float_ret() nounwind {
 ; RV32-ILP32FD-LABEL: caller_float_ret:
 ; RV32-ILP32FD:       # %bb.0:
 ; RV32-ILP32FD-NEXT:    addi sp, sp, -16

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

 }
 
 ; Check lowering of constantpools
 
 define float @lower_constantpool(float %a) nounwind {
 ; RV32I-SMALL-LABEL: lower_constantpool:
 ; RV32I-SMALL:       # %bb.0:
 ; RV32I-SMALL-NEXT:    lui a1, %hi(.LCPI3_0)
-; RV32I-SMALL-NEXT:    addi a1, a1, %lo(.LCPI3_0)
-; RV32I-SMALL-NEXT:    flw ft0, 0(a1)
+; RV32I-SMALL-NEXT:    flw ft0, %lo(.LCPI3_0)(a1)
 ; RV32I-SMALL-NEXT:    fmv.w.x ft1, a0
 ; RV32I-SMALL-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32I-SMALL-NEXT:    fmv.x.w a0, ft0
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_constantpool:
 ; RV32I-MEDIUM:       # %bb.0:
 ; RV32I-MEDIUM-NEXT:  .LBB3_1: # Label of block must be emitted

llvm/test/CodeGen/RISCV/double-imm.ll

 define double @double_imm_op(double %a) nounwind {
 ; RV32IFD-LABEL: double_imm_op:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    fadd.d ft0, ft0, ft1
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: double_imm_op:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV64IFD-NEXT:    addi a1, a1, %lo(.LCPI1_0)
-; RV64IFD-NEXT:    fld ft0, 0(a1)
+; RV64IFD-NEXT:    fld ft0, %lo(.LCPI1_0)(a1)
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, 1.0
   ret double %1
 }

llvm/test/CodeGen/RISCV/double-previous-failure.ll

 ; RV32IFD-NEXT:    sw ra, 12(sp)
 ; RV32IFD-NEXT:    lui a1, 262144
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    call test
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a1, 4(sp)
 ; RV32IFD-NEXT:    fld ft0, 0(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, ft0, ft1
 ; RV32IFD-NEXT:    bnez a0, .LBB1_3
 ; RV32IFD-NEXT:  # %bb.1: # %entry
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_1)
-; RV32IFD-NEXT:    fld ft1, 0(a0)
+; RV32IFD-NEXT:    fld ft1, %lo(.LCPI1_1)(a0)
 ; RV32IFD-NEXT:    flt.d a0, ft1, ft0
 ; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    beqz a0, .LBB1_3
 ; RV32IFD-NEXT:  # %bb.2: # %if.end
 ; RV32IFD-NEXT:    mv a0, zero
 ; RV32IFD-NEXT:    call exit
 ; RV32IFD-NEXT:  .LBB1_3: # %if.then
 ; RV32IFD-NEXT:    call abort

llvm/test/CodeGen/RISCV/float-imm.ll

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a0, 263313
 ; RV32IF-NEXT:    addi a0, a0, -37
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_imm:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI0_0)
-; RV64IF-NEXT:    addi a0, a0, %lo(.LCPI0_0)
-; RV64IF-NEXT:    flw ft0, 0(a0)
+; RV64IF-NEXT:    flw ft0, %lo(.LCPI0_0)(a0)
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   ret float 3.14159274101257324218750
 }
 
 define float @float_imm_op(float %a) nounwind {
-; TODO: addi should be folded in to the flw
 ; RV32IF-LABEL: float_imm_op:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV32IF-NEXT:    addi a1, a1, %lo(.LCPI1_0)
-; RV32IF-NEXT:    flw ft0, 0(a1)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a1)
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_imm_op:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    lui a1, %hi(.LCPI1_0)
-; RV64IF-NEXT:    addi a1, a1, %lo(.LCPI1_0)
-; RV64IF-NEXT:    flw ft0, 0(a1)
+; RV64IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a1)
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }

llvm/test/CodeGen/RISCV/fp-imm.ll

 ; RV64D-NEXT:    ret
   ret float 0.0
 }
 
 define float @f32_negative_zero(float *%pf) nounwind {
 ; RV32F-LABEL: f32_negative_zero:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32F-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32F-NEXT:    flw fa0, 0(a0)
+; RV32F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV32F-NEXT:    ret
 ;
 ; RV32D-LABEL: f32_negative_zero:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV32D-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV32D-NEXT:    flw fa0, 0(a0)
+; RV32D-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV32D-NEXT:    ret
 ;
 ; RV64F-LABEL: f32_negative_zero:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64F-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV64F-NEXT:    flw fa0, 0(a0)
+; RV64F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV64F-NEXT:    ret
 ;
 ; RV64D-LABEL: f32_negative_zero:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    lui a0, %hi(.LCPI1_0)
-; RV64D-NEXT:    addi a0, a0, %lo(.LCPI1_0)
-; RV64D-NEXT:    flw fa0, 0(a0)
+; RV64D-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
 ; RV64D-NEXT:    ret
   ret float -0.0
 }
 
 define double @f64_positive_zero(double *%pd) nounwind {
 ; RV32F-LABEL: f64_positive_zero:
 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    mv a0, zero

 ; RV32F:       # %bb.0:
 ; RV32F-NEXT:    lui a1, 524288
 ; RV32F-NEXT:    mv a0, zero
 ; RV32F-NEXT:    ret
 ;
 ; RV32D-LABEL: f64_negative_zero:
 ; RV32D:       # %bb.0:
 ; RV32D-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV32D-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV32D-NEXT:    fld fa0, 0(a0)
+; RV32D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
 ; RV32D-NEXT:    ret
 ;
 ; RV64F-LABEL: f64_negative_zero:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    addi a0, zero, -1
 ; RV64F-NEXT:    slli a0, a0, 63
 ; RV64F-NEXT:    ret
 ;
 ; RV64D-LABEL: f64_negative_zero:
 ; RV64D:       # %bb.0:
 ; RV64D-NEXT:    lui a0, %hi(.LCPI3_0)
-; RV64D-NEXT:    addi a0, a0, %lo(.LCPI3_0)
-; RV64D-NEXT:    fld fa0, 0(a0)
+; RV64D-NEXT:    fld fa0, %lo(.LCPI3_0)(a0)
 ; RV64D-NEXT:    ret
   ret double -0.0
 }

llvm/test/CodeGen/RISCV/select-const.ll

 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32IF-LABEL: select_const_fp:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    bnez a0, .LBB4_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI4_0)
-; RV32IF-NEXT:    addi a0, a0, %lo(.LCPI4_0)
-; RV32IF-NEXT:    j .LBB4_3
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI4_1)
-; RV32IF-NEXT:    addi a0, a0, %lo(.LCPI4_1)
-; RV32IF-NEXT:  .LBB4_3:
-; RV32IF-NEXT:    flw ft0, 0(a0)
+; RV32IF-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64I-LABEL: select_const_fp:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lui a0, 263168
 ; RV64I-NEXT:    bnez a1, .LBB4_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    lui a0, 264192
 ; RV64I-NEXT:  .LBB4_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: select_const_fp:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    bnez a0, .LBB4_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI4_0)
-; RV64IFD-NEXT:    addi a0, a0, %lo(.LCPI4_0)
-; RV64IFD-NEXT:    j .LBB4_3
+; RV64IFD-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
+; RV64IFD-NEXT:    fmv.x.w a0, ft0
+; RV64IFD-NEXT:    ret
 ; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI4_1)
-; RV64IFD-NEXT:    addi a0, a0, %lo(.LCPI4_1)
-; RV64IFD-NEXT:  .LBB4_3:
-; RV64IFD-NEXT:    flw ft0, 0(a0)
+; RV64IFD-NEXT:    flw ft0, %lo(.LCPI4_1)(a0)
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = select i1 %a, float 3.0, float 4.0
   ret float %1
 }