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[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
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Authored by piotr on Apr 24 2020, 1:33 AM.

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Summary

Frontend guarantees that coherent accesses have
corresponding cache policy bits set (glc, dlc).
Therefore there is no need for extra instructions
that invalidate cache.

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Event Timeline

piotr created this revision.Apr 24 2020, 1:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 24 2020, 1:33 AM
nhaehnle accepted this revision.Apr 24 2020, 4:12 AM
nhaehnle added a reviewer: t-tye.

@t-tye for awareness.

LGTM -- this is a reasonable step to take for us given that the Vulkan memory model has an explicit distinction between Private and NonPrivate memory accesses which we cannot yet model explicitly in LLVM.

This revision is now accepted and ready to land.Apr 24 2020, 4:12 AM
This revision was automatically updated to reflect the committed changes.

@nhaehnle my thinking was that the Vulkan memory model could be semantically represented in the LLVM IR by adding new memory orderings to make the distinction of the effective two sets of memory that the Vulkam memory model introduces. There needs to be memory orderings that only relates to the subset that Vulkan is requiring to be coherent. However, I have not followed the Vulkan memory model specification recently so not sure if it is still the same as when I was looking at it. What are your thoughts?