[AMDGPU] Add the SGPR used for FP copy to block livein lists.

[cdevadas]

Summary

The temporary register used for FP copy
should be live throughout the function.

[arsenm]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

617

Capitalize

llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll

4

Can you add a comment explaining what this tests

[cdevadas]

Added a small description of the test.

[arsenm]

Is this still needed?

[cdevadas]

It has been merged with https://reviews.llvm.org/rG207cd5f68fabbf760c7e66dc6c49e833f3f6f953.

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

void SIFrameLowering::emitPrologue(MachineFunction &MF,
   // turn on all lanes before doing the spill to memory.
   Register ScratchExecCopy;
 
   // Emit the copy if we need an FP, and are using a free SGPR to save it.
   if (FuncInfo->SGPRForFPSaveRestoreCopy) {
     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->SGPRForFPSaveRestoreCopy)
       .addReg(FramePtrReg)
       .setMIFlag(MachineInstr::FrameSetup);
+    // make the register live throughout the function.
+    for (MachineBasicBlock &MBB : MF)
+      MBB.addLiveIn(FuncInfo->SGPRForFPSaveRestoreCopy);
   }
 
   for (const SIMachineFunctionInfo::SGPRSpillVGPRCSR &Reg
          : FuncInfo->getSGPRSpillVGPRs()) {
     if (!Reg.FI.hasValue())
       continue;
 
     if (!ScratchExecCopy) {

llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -stop-after=prologepilog -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+%struct.Data = type { [20 x i32] }
+
+define i32 @fp_save_restore_in_temp_sgpr(%struct.Data addrspace(5)* nocapture readonly byval(%struct.Data) align 4 %arg) #0 {
+  ; GCN-LABEL: name: fp_save_restore_in_temp_sgpr
+  ; GCN: bb.0.begin:
+  ; GCN:   liveins: $sgpr30_sgpr31, $sgpr7
+  ; GCN:   $sgpr7 = frame-setup COPY $sgpr33
+  ; GCN:   $sgpr33 = frame-setup COPY $sgpr32
+  ; GCN: bb.1.lp_end:
+  ; GCN:   liveins: $sgpr6, $vgpr1, $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31, $sgpr7
+  ; GCN: bb.2.lp_begin:
+  ; GCN:   liveins: $sgpr6, $vgpr1, $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr30_sgpr31, $sgpr7
+  ; GCN: bb.3.Flow:
+  ; GCN:   liveins: $sgpr6, $vgpr0, $vgpr1, $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31, $sgpr7
+  ; GCN: bb.4.end:
+  ; GCN:   liveins: $vgpr0, $sgpr4_sgpr5, $sgpr30_sgpr31, $sgpr7
+  ; GCN:   $sgpr33 = frame-setup COPY $sgpr7
+begin:
+  br label %lp_begin
+
+lp_end:                                                ; preds = %lp_begin
+  %cur_idx = add nuw nsw i32 %idx, 1
+  %lp_term_cond = icmp eq i32 %cur_idx, 20
+  br i1 %lp_term_cond, label %end, label %lp_begin
+
+lp_begin:                                                ; preds = %lp_end, %begin
+  %idx = phi i32 [ 0, %begin ], [ %cur_idx, %lp_end ]
+  %ptr = getelementptr inbounds %struct.Data, %struct.Data addrspace(5)* %arg, i32 0, i32 0, i32 %idx
+  %data = load i32, i32 addrspace(5)* %ptr, align 4
+  %data_cmp = icmp eq i32 %data, %idx
+  br i1 %data_cmp, label %lp_end, label %end
+
+end:                                               ; preds = %lp_end, %lp_begin
+  %ret_val = phi i32 [ 0, %lp_begin ], [ 1, %lp_end ]
+  ret i32 %ret_val
+}
+
+attributes #0 = { norecurse nounwind "frame-pointer"="all" }