Fix intra-tile upper bound setting in a scenario where the tile size was
larger than the trip count.
Details
Details
Diff Detail
Diff Detail
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Buildable 53977 Build 61778: arc lint + arc unit
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[MLIR] Fix affine loop tiling utility upper bound bug ClosedPublic Authored by bondhugula on Apr 20 2020, 10:01 AM.
Details Summary Fix intra-tile upper bound setting in a scenario where the tile size was
Diff Detail
Event TimelineThis revision is now accepted and ready to land.Apr 20 2020, 11:37 AM Closed by commit rG3dff8c9109a7: [MLIR] Fix affine loop tiling utility upper bound bug (authored by bondhugula). · Explain WhyApr 20 2020, 12:28 PM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 258781 mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp
mlir/test/Dialect/Affine/loop-tiling.mlir
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