[VE] Add alternative names to registers

[kaz7]

Summary

VE uses identical names "%s0-63" to all generic registers. Change to use
alternative name mechanism among all generic registers instead of hard-
coding them.

[kaz7]

This time, I am using new feature so I would like to add reviewers who know about it.

[simoll]

In D78174#1982544, @kaz7 wrote:

This time, I am using new feature so I would like to add reviewers who know about it.

Makes sense.

One thing i noted, which should not go into this patch and is more of a cleanup thing: we probably want register name aliases also on the c++ side (eg something like VE::SP to refer to the stack pointer instead of using its SX register number).

[kaz7]

Modify include path to try to avoid clang-tidy error.

[simoll]

Ping @arsenm . Do you have any concerns with the use of altNames here?

[arsenm]

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

39–41

Typo regitster

llvm/lib/Target/VE/VERegisterInfo.td

39

You can just lower case the original names unless you want to handle printing both capital and upper case for some reason

[kaz7]

Update code to follow @arsenm comments.

[kaz7]

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

39–41

Thank you. Corrected it.

llvm/lib/Target/VE/VERegisterInfo.td

39

Thanks. Changed to use lower case in string representations.

[arsenm]

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

41

You should be able to directly use the output of getRegisterName without the lower now?

[kaz7]

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

41

That's true. I haven't noticed it. Thank you for very useful comments to reduce computation time. I really appreciate it.

[kaz7]

Remove lower() by lowering register name defined in VERegisterInfo.td.
Following an @arsenm suggesntion. Thanks!

[arsenm]

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

41

You don't need to construct a stringref either

[kaz7]

Removed StringRef constructor by following arsenm suggestion. Thanks!
Rebased to the latest master.

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h

 //===-- VEInstPrinter.h - Convert VE MCInst to assembly syntax ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints an VE MCInst to a .s file.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_VE_INSTPRINTER_VEINSTPRINTER_H
 #define LLVM_LIB_TARGET_VE_INSTPRINTER_VEINSTPRINTER_H
 
+#include "VEMCTargetDesc.h"
 #include "llvm/MC/MCInstPrinter.h"
 
 namespace llvm {
 
 class VEInstPrinter : public MCInstPrinter {
 public:
   VEInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                 const MCRegisterInfo &MRI)
       : MCInstPrinter(MAI, MII, MRI) {}
 
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &OS) override;
 
   // Autogenerated by tblgen.
   bool printAliasInstr(const MCInst *, uint64_t Address,
                        const MCSubtargetInfo &, raw_ostream &);
   void printInstruction(const MCInst *, uint64_t, const MCSubtargetInfo &,
                         raw_ostream &);
-  static const char *getRegisterName(unsigned RegNo);
+  static const char *getRegisterName(unsigned RegNo,
+                                     unsigned AltIdx = VE::NoRegAltName);
 
   void printOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
                     raw_ostream &OS);
   void printMemASXOperand(const MCInst *MI, int OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &OS,
                           const char *Modifier = nullptr);
   void printMemASOperandASX(const MCInst *MI, int OpNum,
                             const MCSubtargetInfo &STI, raw_ostream &OS,

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

 }
 } // namespace llvm
 
 #define GET_INSTRUCTION_NAME
 #define PRINT_ALIAS_INSTR
 #include "VEGenAsmWriter.inc"
 
 void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << '%' << StringRef(getRegisterName(RegNo)).lower();
+  // Generic registers have identical register name among register classes.
+  unsigned AltIdx = VE::AsmName;
+  OS << '%' << StringRef(getRegisterName(RegNo, AltIdx)).lower();
 }
 
 void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                               StringRef Annot, const MCSubtargetInfo &STI,
                               raw_ostream &OS) {
   if (!printAliasInstr(MI, Address, STI, OS))
     printInstruction(MI, Address, STI, OS);
   printAnnotation(OS, Annot);

llvm/lib/Target/VE/VERegisterInfo.td

 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 //  Declarations that describe the VE register file
 //===----------------------------------------------------------------------===//
 
-class VEReg<bits<7> Enc, string n> : Register<n> {
+class VEReg<bits<7> enc, string n, list<Register> subregs = [],
+            list<string> altNames = [], list<Register> aliases = []>
+        : Register<n, altNames> {
   let HWEncoding{15-7} = 0;
-  let HWEncoding{6-0} = Enc;
+  let HWEncoding{6-0} = enc;
   let Namespace = "VE";
+  let SubRegs = subregs;
+  let Aliases = aliases;
 }
 
 let Namespace = "VE" in {
   def sub_i8      : SubRegIndex<8, 56>;         // Low 8 bit (56..63)
   def sub_i16     : SubRegIndex<16, 48>;        // Low 16 bit (48..63)
   def sub_i32     : SubRegIndex<32, 32>;        // Low 32 bit (32..63)
   def sub_f32     : SubRegIndex<32>;            // High 32 bit (0..31)
+  def AsmName     : RegAltNameIndex;
 }
 
-// Registers are identified with 7-bit ID numbers.
-// R - 64-bit integer or floating-point registers
-class R<bits<7> Enc, string n, list<Register> subregs = [],
-        list<Register> aliases = []>: VEReg<Enc, n> {
-  let SubRegs = subregs;
-  let Aliases = aliases;
-}
+//-----------------------------------------------------------------------------
+// Gneric Registers
+//-----------------------------------------------------------------------------
+
+let RegAltNameIndices = [AsmName] in {
 
 // Generic integer registers - 8 bits wide
 foreach I = 0-63 in
-  def SB#I : R<I, "S"#I>, DwarfRegNum<[I]>;
+  def SB#I : VEReg<I, "sb"#I, [], ["s"#I]>, DwarfRegNum<[I]>;
 
 // Generic integer registers - 16 bits wide
 let SubRegIndices = [sub_i8] in
 foreach I = 0-63 in
-  def SH#I : R<I, "S"#I, [!cast<R>("SB"#I)]>, DwarfRegNum<[I]>;
+  def SH#I : VEReg<I, "sh"#I, [!cast<VEReg>("SB"#I)], ["s"#I]>,
+                   DwarfRegNum<[I]>;
 
 // Generic integer registers - 32 bits wide
 let SubRegIndices = [sub_i16] in
 foreach I = 0-63 in
-  def SW#I : R<I, "S"#I, [!cast<R>("SH"#I)]>, DwarfRegNum<[I]>;
+  def SW#I : VEReg<I, "sw"#I, [!cast<VEReg>("SH"#I)], ["s"#I]>,
+                   DwarfRegNum<[I]>;
 
 // Generic floating point registers - 32 bits wide
 //   NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation
 //         problem.
 foreach I = 0-63 in
-  def SF#I : R<I, "S"#I, [], [!cast<R>("SW"#I)]>, DwarfRegNum<[I]>;
+  def SF#I : VEReg<I, "sf"#I, [], ["s"#I], [!cast<VEReg>("SW"#I)]>,
+                   DwarfRegNum<[I]>;
 
 // Generic integer registers - 64 bits wide
 let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in
 foreach I = 0-63 in
-  def SX#I : R<I, "S"#I, [!cast<R>("SW"#I), !cast<R>("SF"#I)]>,
-             DwarfRegNum<[I]>;
+  def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
+                   ["s"#I]>, DwarfRegNum<[I]>;
+
+} // RegAltNameIndices = [AsmName]
 
 // Register classes.
 //
 // The register order is defined in terms of the preferred
 // allocation order.
 def I8  : RegisterClass<"VE", [i8], 8,
                         (add (sequence "SB%u", 0, 7),
                              (sequence "SB%u", 34, 63),