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Differential D77595

[SveEmitter] Add builtins for svwhile
ClosedPublic

Authored by sdesmalen on Apr 6 2020, 3:14 PM.

Details

Reviewers
SjoerdMeijer
efriedma
rovka
Commits
rG1559485e6002: [SveEmitter] Add builtins for svwhile
Summary

This also adds the IsOverloadWhile flag which tells CGBuiltin to use
both the default type (predicate) and the type of the second operand
(scalar) as the overloaded types for the LLMV IR intrinsic.

Diff Detail

Event Timeline

sdesmalen created this revision.Apr 6 2020, 3:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2020, 3:14 PM
Herald added a subscriber: tschuett. · View Herald Transcript
sdesmalen added a parent revision: D77594: [SveEmitter] Add support for _n form builtins.Apr 6 2020, 3:14 PM
sdesmalen added a child revision: D77596: [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat.
Harbormaster failed remote builds in B52052: Diff 255507!Apr 6 2020, 3:49 PM
sdesmalen updated this revision to Diff 257829.Apr 15 2020, 1:40 PM
sdesmalen retitled this revision from [SveEmitter] Add NoAuto flag and builtins for svwhile. to [SveEmitter] Add builtins for svwhile.
sdesmalen edited the summary of this revision. (Show Details)
  • The function that returns a list of overloaded types for the intrinsics added in D77596 means we don't need to use custom codegen for the while intrinsics any more.
sdesmalen removed a child revision: D77596: [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat.Apr 15 2020, 1:41 PM
sdesmalen added a parent revision: D77596: [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat.
sdesmalen added a child revision: D78238: [SveEmitter] Add builtins for svwhilerw/svwhilewr.
efriedma accepted this revision.Apr 15 2020, 2:41 PM

LGTM

This revision is now accepted and ready to land.Apr 15 2020, 2:41 PM
Closed by commit rG1559485e6002: [SveEmitter] Add builtins for svwhile (authored by sdesmalen). · Explain WhyApr 22 2020, 2:09 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
1 line
30 lines
lib/
CodeGen/
79 lines
test/
CodeGen/
aarch64-sve-intrinsics/
151 lines
151 lines
aarch64-sve2-intrinsics/
185 lines
185 lines
utils/
TableGen/
21 lines

Diff 255507

clang/include/clang/Basic/TargetBuiltins.h

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Lines#undef LLVM_GET_SVE_IMMCHECKTYPES
bool isLoad() const { return Flags & IsLoad; } bool isLoad() const { return Flags & IsLoad; }
bool isStore() const { return Flags & IsStore; } bool isStore() const { return Flags & IsStore; }
bool isGatherLoad() const { return Flags & IsGatherLoad; } bool isGatherLoad() const { return Flags & IsGatherLoad; }
bool isScatterStore() const { return Flags & IsScatterStore; } bool isScatterStore() const { return Flags & IsScatterStore; }
bool isStructLoad() const { return Flags & IsStructLoad; } bool isStructLoad() const { return Flags & IsStructLoad; }
bool isStructStore() const { return Flags & IsStructStore; } bool isStructStore() const { return Flags & IsStructStore; }
bool isZExtReturn() const { return Flags & IsZExtReturn; } bool isZExtReturn() const { return Flags & IsZExtReturn; }
bool isNoAuto() const { return Flags & NoAuto; }
uint64_t getBits() const { return Flags; } uint64_t getBits() const { return Flags; }
bool isFlagSet(uint64_t Flag) const { return Flags & Flag; } bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
}; };
/// Hexagon builtins /// Hexagon builtins
namespace Hexagon { namespace Hexagon {
enum { enum {
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

clang/include/clang/Basic/arm_sve.td

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
// P: predicate type // P: predicate type
// a: scalar of element type (splat to vector type) // a: scalar of element type (splat to vector type)
// e: 1/2 width unsigned elements, 2x element count // e: 1/2 width unsigned elements, 2x element count
// h: 1/2 width elements, 2x element count // h: 1/2 width elements, 2x element count
// q: 1/4 width elements, 4x element count // q: 1/4 width elements, 4x element count
// o: 4x width elements, 1/4 element count // o: 4x width elements, 1/4 element count
// //
// i: constant uint64_t // i: constant uint64_t
// k: int32_t
// l: int64_t
// m: uint32_t
// n: uint64_t
// //
// I: Predicate Pattern (sv_pattern) // I: Predicate Pattern (sv_pattern)
// l: int64_t // l: int64_t
// A: pointer to int8_t // A: pointer to int8_t
// B: pointer to int16_t // B: pointer to int16_t
// C: pointer to int32_t // C: pointer to int32_t
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
def SplatOperandMask : FlagType<0x00001C00>; def SplatOperandMask : FlagType<0x00001C00>;
def IsLoad : FlagType<0x00002000>; def IsLoad : FlagType<0x00002000>;
def IsStore : FlagType<0x00004000>; def IsStore : FlagType<0x00004000>;
def IsGatherLoad : FlagType<0x00008000>; def IsGatherLoad : FlagType<0x00008000>;
def IsScatterStore : FlagType<0x00010000>; def IsScatterStore : FlagType<0x00010000>;
def IsStructLoad : FlagType<0x00020000>; def IsStructLoad : FlagType<0x00020000>;
def IsStructStore : FlagType<0x00040000>; def IsStructStore : FlagType<0x00040000>;
def IsZExtReturn : FlagType<0x00080000>; // Return value is sign-extend by default def IsZExtReturn : FlagType<0x00080000>; // Return value is sign-extend by default
def NoAuto : FlagType<0x00100000>;
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
class ImmCheckType<int val> { class ImmCheckType<int val> {
int Value = val; int Value = val;
} }
def ImmCheck0_31 : ImmCheckType<0>; // 0..31 (used for e.g. predicate patterns) def ImmCheck0_31 : ImmCheckType<0>; // 0..31 (used for e.g. predicate patterns)
def ImmCheck1_16 : ImmCheckType<1>; // 1..16 def ImmCheck1_16 : ImmCheckType<1>; // 1..16
def ImmCheckExtract : ImmCheckType<2>; // 0..(2048/sizeinbits(elt) - 1) def ImmCheckExtract : ImmCheckType<2>; // 0..(2048/sizeinbits(elt) - 1)
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// SVE2 - Uniform DSP operations // SVE2 - Uniform DSP operations
let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in { let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
def SVQSHLU_M : SInst<"svqshlu[_n_{d}]", "uPdi", "csil", MergeOp1, "aarch64_sve_sqshlu", [], [ImmCheck<2, ImmCheckShiftLeft, 1>]>; def SVQSHLU_M : SInst<"svqshlu[_n_{d}]", "uPdi", "csil", MergeOp1, "aarch64_sve_sqshlu", [], [ImmCheck<2, ImmCheckShiftLeft, 1>]>;
} }
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// While comparisons
def SVWHILELE_S32 : SInst<"svwhilele_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilele", [NoAuto]>;
def SVWHILELE_S64 : SInst<"svwhilele_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilele", [NoAuto]>;
def SVWHILELO_U32 : SInst<"svwhilelt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilelo", [NoAuto]>;
def SVWHILELO_U64 : SInst<"svwhilelt_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilelo", [NoAuto]>;
def SVWHILELS_U32 : SInst<"svwhilele_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilels", [NoAuto]>;
def SVWHILELS_U64 : SInst<"svwhilele_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilels", [NoAuto]>;
def SVWHILELT_S32 : SInst<"svwhilelt_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt", [NoAuto]>;
def SVWHILELT_S64 : SInst<"svwhilelt_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilelt", [NoAuto]>;
////////////////////////////////////////////////////////////////////////////////
// Floating-point arithmetic // Floating-point arithmetic
defm SVABS_F : SInstZPZ<"svabs", "hfd", "aarch64_sve_fabs">; defm SVABS_F : SInstZPZ<"svabs", "hfd", "aarch64_sve_fabs">;
defm SVNEG_F : SInstZPZ<"svneg", "hfd", "aarch64_sve_fneg">; defm SVNEG_F : SInstZPZ<"svneg", "hfd", "aarch64_sve_fneg">;
def SVTMAD : SInst<"svtmad[_{d}]", "dddi", "hfd", MergeNone, "aarch64_sve_ftmad_x", [], [ImmCheck<2, ImmCheck0_7>]>; def SVTMAD : SInst<"svtmad[_{d}]", "dddi", "hfd", MergeNone, "aarch64_sve_ftmad_x", [], [ImmCheck<2, ImmCheck0_7>]>;
def SVMLA_LANE : SInst<"svmla_lane[_{d}]", "ddddi", "hfd", MergeNone, "aarch64_sve_fmla_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>; def SVMLA_LANE : SInst<"svmla_lane[_{d}]", "ddddi", "hfd", MergeNone, "aarch64_sve_fmla_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
def SVCMLA_LANE : SInst<"svcmla_lane[_{d}]", "ddddii", "hf", MergeNone, "aarch64_sve_fcmla_lane", [], [ImmCheck<3, ImmCheckLaneIndexCompRotate, 2>, def SVCMLA_LANE : SInst<"svcmla_lane[_{d}]", "ddddii", "hf", MergeNone, "aarch64_sve_fcmla_lane", [], [ImmCheck<3, ImmCheckLaneIndexCompRotate, 2>,
ImmCheck<4, ImmCheckComplexRotAll90>]>; ImmCheck<4, ImmCheckComplexRotAll90>]>;
def SVCADD_M : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeOp1, "aarch64_sve_fcadd", [], [ImmCheck<3, ImmCheckComplexRot90_270>]>; def SVCADD_M : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeOp1, "aarch64_sve_fcadd", [], [ImmCheck<3, ImmCheckComplexRot90_270>]>;
def SVCMLA_M : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeOp1, "aarch64_sve_fcmla", [], [ImmCheck<4, ImmCheckComplexRotAll90>]>; def SVCMLA_M : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeOp1, "aarch64_sve_fcmla", [], [ImmCheck<4, ImmCheckComplexRotAll90>]>;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Saturating scalar arithmetic // Saturating scalar arithmetic
def SVQDECH_S : SInst<"svqdech_pat[_{d}]", "ddIi", "s", MergeNone, "aarch64_sve_sqdech", [], [ImmCheck<2, ImmCheck1_16>]>; def SVQDECH_S : SInst<"svqdech_pat[_{d}]", "ddIi", "s", MergeNone, "aarch64_sve_sqdech", [], [ImmCheck<2, ImmCheck1_16>]>;
def SVQDECH_U : SInst<"svqdech_pat[_{d}]", "ddIi", "Us", MergeNone, "aarch64_sve_uqdech", [], [ImmCheck<2, ImmCheck1_16>]>; def SVQDECH_U : SInst<"svqdech_pat[_{d}]", "ddIi", "Us", MergeNone, "aarch64_sve_uqdech", [], [ImmCheck<2, ImmCheck1_16>]>;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Integer arithmetic // Integer arithmetic
def SVDOT_LANE_S : SInst<"svdot_lane[_{d}]", "ddqqi", "il", MergeNone, "aarch64_sve_sdot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; def SVDOT_LANE_S : SInst<"svdot_lane[_{d}]", "ddqqi", "il", MergeNone, "aarch64_sve_sdot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>;
def SVDOT_LANE_U : SInst<"svdot_lane[_{d}]", "ddqqi", "UiUl", MergeNone, "aarch64_sve_udot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; def SVDOT_LANE_U : SInst<"svdot_lane[_{d}]", "ddqqi", "UiUl", MergeNone, "aarch64_sve_udot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>;
////////////////////////////////////////////////////////////////////////////////
// SVE2 WhileGE/GT
let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
def SVWHILEGE_S32 : SInst<"svwhilege_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilege", [NoAuto]>;
def SVWHILEGE_S64 : SInst<"svwhilege_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilege", [NoAuto]>;
def SVWHILEGT_S32 : SInst<"svwhilegt_{d}[_{1}]", "Pkk", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt", [NoAuto]>;
def SVWHILEGT_S64 : SInst<"svwhilegt_{d}[_{1}]", "Pll", "PcPsPiPl", MergeNone, "aarch64_sve_whilegt", [NoAuto]>;
def SVWHILEHI_U32 : SInst<"svwhilegt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [NoAuto]>;
def SVWHILEHI_U64 : SInst<"svwhilegt_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [NoAuto]>;
def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [NoAuto]>;
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [NoAuto]>;
}

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,619 Lines • ▼ Show 20 Lines auto *Builtin = findARMVectorIntrinsicInMap(AArch64SVEIntrinsicMap, BuiltinID,
AArch64SVEIntrinsicsProvenSorted); AArch64SVEIntrinsicsProvenSorted);
SVETypeFlags TypeFlags(Builtin->TypeModifier); SVETypeFlags TypeFlags(Builtin->TypeModifier);
llvm::Type *Ty = ConvertType(E->getType()); llvm::Type *Ty = ConvertType(E->getType());
if (TypeFlags.isLoad()) if (TypeFlags.isLoad())
return EmitSVEMaskedLoad(E, Ty, Ops, Builtin->LLVMIntrinsic, return EmitSVEMaskedLoad(E, Ty, Ops, Builtin->LLVMIntrinsic,
TypeFlags.isZExtReturn()); TypeFlags.isZExtReturn());
else if (TypeFlags.isStore()) else if (TypeFlags.isStore())
return EmitSVEMaskedStore(E, Ops, Builtin->LLVMIntrinsic); return EmitSVEMaskedStore(E, Ops, Builtin->LLVMIntrinsic);
else if (Builtin->LLVMIntrinsic != 0) { else if (Builtin->LLVMIntrinsic != 0 && !TypeFlags.isNoAuto()) {
llvm::Type* OverloadedTy = getSVEType(TypeFlags); llvm::Type* OverloadedTy = getSVEType(TypeFlags);
if (TypeFlags.getMergeType() == SVETypeFlags::MergeZeroExp) if (TypeFlags.getMergeType() == SVETypeFlags::MergeZeroExp)
InsertExplicitZeroOperand(Builder, Ty, Ops); InsertExplicitZeroOperand(Builder, Ty, Ops);
if (TypeFlags.getMergeType() == SVETypeFlags::MergeAnyExp) if (TypeFlags.getMergeType() == SVETypeFlags::MergeAnyExp)
InsertExplicitUndefOperand(Builder, Ty, Ops); InsertExplicitUndefOperand(Builder, Ty, Ops);
Show All 18 Lines if (TypeFlags.getMergeType() == SVETypeFlags::MergeZero) {
Ops[1] = Builder.CreateSelect(Ops[0], Ops[1], SplatZero); Ops[1] = Builder.CreateSelect(Ops[0], Ops[1], SplatZero);
} }
Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, OverloadedTy); Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, OverloadedTy);
Value *Call = Builder.CreateCall(F, Ops); Value *Call = Builder.CreateCall(F, Ops);
return Call; return Call;
} }
switch (BuiltinID) {
default:
return nullptr;
case SVE::BI__builtin_sve_svwhilele_b8_s32:
case SVE::BI__builtin_sve_svwhilele_b8_s64:
case SVE::BI__builtin_sve_svwhilele_b8_u32:
case SVE::BI__builtin_sve_svwhilele_b8_u64:
case SVE::BI__builtin_sve_svwhilele_b16_s32:
case SVE::BI__builtin_sve_svwhilele_b16_s64:
case SVE::BI__builtin_sve_svwhilele_b16_u32:
case SVE::BI__builtin_sve_svwhilele_b16_u64:
case SVE::BI__builtin_sve_svwhilele_b32_s32:
case SVE::BI__builtin_sve_svwhilele_b32_s64:
case SVE::BI__builtin_sve_svwhilele_b32_u32:
case SVE::BI__builtin_sve_svwhilele_b32_u64:
case SVE::BI__builtin_sve_svwhilele_b64_s32:
case SVE::BI__builtin_sve_svwhilele_b64_s64:
case SVE::BI__builtin_sve_svwhilele_b64_u32:
case SVE::BI__builtin_sve_svwhilele_b64_u64:
case SVE::BI__builtin_sve_svwhilelt_b8_s32:
case SVE::BI__builtin_sve_svwhilelt_b8_s64:
case SVE::BI__builtin_sve_svwhilelt_b8_u32:
case SVE::BI__builtin_sve_svwhilelt_b8_u64:
case SVE::BI__builtin_sve_svwhilelt_b16_s32:
case SVE::BI__builtin_sve_svwhilelt_b16_s64:
case SVE::BI__builtin_sve_svwhilelt_b16_u32:
case SVE::BI__builtin_sve_svwhilelt_b16_u64:
case SVE::BI__builtin_sve_svwhilelt_b32_s32:
case SVE::BI__builtin_sve_svwhilelt_b32_s64:
case SVE::BI__builtin_sve_svwhilelt_b32_u32:
case SVE::BI__builtin_sve_svwhilelt_b32_u64:
case SVE::BI__builtin_sve_svwhilelt_b64_s32:
case SVE::BI__builtin_sve_svwhilelt_b64_s64:
case SVE::BI__builtin_sve_svwhilelt_b64_u32:
case SVE::BI__builtin_sve_svwhilelt_b64_u64:
case SVE::BI__builtin_sve_svwhilege_b8_s32:
case SVE::BI__builtin_sve_svwhilege_b8_s64:
case SVE::BI__builtin_sve_svwhilege_b8_u32:
case SVE::BI__builtin_sve_svwhilege_b8_u64:
case SVE::BI__builtin_sve_svwhilege_b16_s32:
case SVE::BI__builtin_sve_svwhilege_b16_s64:
case SVE::BI__builtin_sve_svwhilege_b16_u32:
case SVE::BI__builtin_sve_svwhilege_b16_u64:
case SVE::BI__builtin_sve_svwhilege_b32_s32:
case SVE::BI__builtin_sve_svwhilege_b32_s64:
case SVE::BI__builtin_sve_svwhilege_b32_u32:
case SVE::BI__builtin_sve_svwhilege_b32_u64:
case SVE::BI__builtin_sve_svwhilege_b64_s32:
case SVE::BI__builtin_sve_svwhilege_b64_s64:
case SVE::BI__builtin_sve_svwhilege_b64_u32:
case SVE::BI__builtin_sve_svwhilege_b64_u64:
case SVE::BI__builtin_sve_svwhilegt_b8_s32:
case SVE::BI__builtin_sve_svwhilegt_b8_s64:
case SVE::BI__builtin_sve_svwhilegt_b8_u32:
case SVE::BI__builtin_sve_svwhilegt_b8_u64:
case SVE::BI__builtin_sve_svwhilegt_b16_s32:
case SVE::BI__builtin_sve_svwhilegt_b16_s64:
case SVE::BI__builtin_sve_svwhilegt_b16_u32:
case SVE::BI__builtin_sve_svwhilegt_b16_u64:
case SVE::BI__builtin_sve_svwhilegt_b32_s32:
case SVE::BI__builtin_sve_svwhilegt_b32_s64:
case SVE::BI__builtin_sve_svwhilegt_b32_u32:
case SVE::BI__builtin_sve_svwhilegt_b32_u64:
case SVE::BI__builtin_sve_svwhilegt_b64_s32:
case SVE::BI__builtin_sve_svwhilegt_b64_s64:
case SVE::BI__builtin_sve_svwhilegt_b64_u32:
case SVE::BI__builtin_sve_svwhilegt_b64_u64: {
SVETypeFlags TypeFlags(Builtin->TypeModifier);
llvm::Type *RetTy = getSVEType(TypeFlags);
llvm::Type *ArgTypes[] = {RetTy, Ops[1]->getType()};
Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, ArgTypes);
Value *Call = Builder.CreateCall(F, Ops);
return EmitSVEPredicateCast(Call, cast<llvm::VectorType>(Ty));
}
}
/// Should not happen /// Should not happen
return nullptr; return nullptr;
} }
Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
const CallExpr *E, const CallExpr *E,
llvm::Triple::ArchType Arch) { llvm::Triple::ArchType Arch) {
if (BuiltinID >= AArch64::FirstSVEBuiltin && if (BuiltinID >= AArch64::FirstSVEBuiltin &&
▲ Show 20 Lines • Show All 8,027 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c

  • This file was added.
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
svbool_t test_svwhilele_b8_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilele_b8_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilele_b8,_s32,,)(op1, op2);
}
svbool_t test_svwhilele_b16_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilele_b16_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b16,_s32,,)(op1, op2);
}
svbool_t test_svwhilele_b32_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilele_b32_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b32,_s32,,)(op1, op2);
}
svbool_t test_svwhilele_b64_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilele_b64_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b64,_s32,,)(op1, op2);
}
svbool_t test_svwhilele_b8_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilele_b8_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilele_b8,_u32,,)(op1, op2);
}
svbool_t test_svwhilele_b16_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilele_b16_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b16,_u32,,)(op1, op2);
}
svbool_t test_svwhilele_b32_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilele_b32_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b32,_u32,,)(op1, op2);
}
svbool_t test_svwhilele_b64_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilele_b64_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b64,_u32,,)(op1, op2);
}
svbool_t test_svwhilele_b8_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilele_b8_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilele_b8,_s64,,)(op1, op2);
}
svbool_t test_svwhilele_b16_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilele_b16_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b16,_s64,,)(op1, op2);
}
svbool_t test_svwhilele_b32_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilele_b32_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b32,_s64,,)(op1, op2);
}
svbool_t test_svwhilele_b64_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilele_b64_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b64,_s64,,)(op1, op2);
}
svbool_t test_svwhilele_b8_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilele_b8_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilele_b8,_u64,,)(op1, op2);
}
svbool_t test_svwhilele_b16_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilele_b16_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilels.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b16,_u64,,)(op1, op2);
}
svbool_t test_svwhilele_b32_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilele_b32_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilels.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b32,_u64,,)(op1, op2);
}
svbool_t test_svwhilele_b64_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilele_b64_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilels.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilele_b64,_u64,,)(op1, op2);
}

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c

  • This file was added.
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
svbool_t test_svwhilelt_b8_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b8_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilelt_b8,_s32,,)(op1, op2);
}
svbool_t test_svwhilelt_b16_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b16_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b16,_s32,,)(op1, op2);
}
svbool_t test_svwhilelt_b32_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b32_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b32,_s32,,)(op1, op2);
}
svbool_t test_svwhilelt_b64_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b64_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b64,_s32,,)(op1, op2);
}
svbool_t test_svwhilelt_b8_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b8_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilelt_b8,_u32,,)(op1, op2);
}
svbool_t test_svwhilelt_b16_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b16_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b16,_u32,,)(op1, op2);
}
svbool_t test_svwhilelt_b32_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b32_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b32,_u32,,)(op1, op2);
}
svbool_t test_svwhilelt_b64_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilelt_b64_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b64,_u32,,)(op1, op2);
}
svbool_t test_svwhilelt_b8_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b8_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilelt_b8,_s64,,)(op1, op2);
}
svbool_t test_svwhilelt_b16_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b16_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b16,_s64,,)(op1, op2);
}
svbool_t test_svwhilelt_b32_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b32_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b32,_s64,,)(op1, op2);
}
svbool_t test_svwhilelt_b64_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b64_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b64,_s64,,)(op1, op2);
}
svbool_t test_svwhilelt_b8_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b8_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
return SVE_ACLE_FUNC(svwhilelt_b8,_u64,,)(op1, op2);
}
svbool_t test_svwhilelt_b16_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b16_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b16,_u64,,)(op1, op2);
}
svbool_t test_svwhilelt_b32_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b32_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b32,_u64,,)(op1, op2);
}
svbool_t test_svwhilelt_b64_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilelt_b64_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
return SVE_ACLE_FUNC(svwhilelt_b64,_u64,,)(op1, op2);
}

clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilege.c

  • This file was added.
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
#include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
svbool_t test_svwhilege_b8_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilege_b8_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b8_s32'}}
return SVE_ACLE_FUNC(svwhilege_b8,_s32,,)(op1, op2);
}
svbool_t test_svwhilege_b16_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilege_b16_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b16_s32'}}
return SVE_ACLE_FUNC(svwhilege_b16,_s32,,)(op1, op2);
}
svbool_t test_svwhilege_b32_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilege_b32_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b32_s32'}}
return SVE_ACLE_FUNC(svwhilege_b32,_s32,,)(op1, op2);
}
svbool_t test_svwhilege_b64_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilege_b64_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b64_s32'}}
return SVE_ACLE_FUNC(svwhilege_b64,_s32,,)(op1, op2);
}
svbool_t test_svwhilege_b8_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilege_b8_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b8_u32'}}
return SVE_ACLE_FUNC(svwhilege_b8,_u32,,)(op1, op2);
}
svbool_t test_svwhilege_b16_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilege_b16_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b16_u32'}}
return SVE_ACLE_FUNC(svwhilege_b16,_u32,,)(op1, op2);
}
svbool_t test_svwhilege_b32_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilege_b32_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b32_u32'}}
return SVE_ACLE_FUNC(svwhilege_b32,_u32,,)(op1, op2);
}
svbool_t test_svwhilege_b64_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilege_b64_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b64_u32'}}
return SVE_ACLE_FUNC(svwhilege_b64,_u32,,)(op1, op2);
}
svbool_t test_svwhilege_b8_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilege_b8_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b8_s64'}}
return SVE_ACLE_FUNC(svwhilege_b8,_s64,,)(op1, op2);
}
svbool_t test_svwhilege_b16_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilege_b16_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b16_s64'}}
return SVE_ACLE_FUNC(svwhilege_b16,_s64,,)(op1, op2);
}
svbool_t test_svwhilege_b32_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilege_b32_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b32_s64'}}
return SVE_ACLE_FUNC(svwhilege_b32,_s64,,)(op1, op2);
}
svbool_t test_svwhilege_b64_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilege_b64_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b64_s64'}}
return SVE_ACLE_FUNC(svwhilege_b64,_s64,,)(op1, op2);
}
svbool_t test_svwhilege_b8_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilege_b8_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b8_u64'}}
return SVE_ACLE_FUNC(svwhilege_b8,_u64,,)(op1, op2);
}
svbool_t test_svwhilege_b16_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilege_b16_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b16_u64'}}
return SVE_ACLE_FUNC(svwhilege_b16,_u64,,)(op1, op2);
}
svbool_t test_svwhilege_b32_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilege_b32_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b32_u64'}}
return SVE_ACLE_FUNC(svwhilege_b32,_u64,,)(op1, op2);
}
svbool_t test_svwhilege_b64_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilege_b64_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilege_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilege_b64_u64'}}
return SVE_ACLE_FUNC(svwhilege_b64,_u64,,)(op1, op2);
}

clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c

  • This file was added.
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
#include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
svbool_t test_svwhilegt_b8_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b8_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_s32'}}
return SVE_ACLE_FUNC(svwhilegt_b8,_s32,,)(op1, op2);
}
svbool_t test_svwhilegt_b16_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b16_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b16_s32'}}
return SVE_ACLE_FUNC(svwhilegt_b16,_s32,,)(op1, op2);
}
svbool_t test_svwhilegt_b32_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b32_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b32_s32'}}
return SVE_ACLE_FUNC(svwhilegt_b32,_s32,,)(op1, op2);
}
svbool_t test_svwhilegt_b64_s32(int32_t op1, int32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b64_s32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b64_s32'}}
return SVE_ACLE_FUNC(svwhilegt_b64,_s32,,)(op1, op2);
}
svbool_t test_svwhilegt_b8_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b8_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32 %op1, i32 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_u32'}}
return SVE_ACLE_FUNC(svwhilegt_b8,_u32,,)(op1, op2);
}
svbool_t test_svwhilegt_b16_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b16_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b16_u32'}}
return SVE_ACLE_FUNC(svwhilegt_b16,_u32,,)(op1, op2);
}
svbool_t test_svwhilegt_b32_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b32_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b32_u32'}}
return SVE_ACLE_FUNC(svwhilegt_b32,_u32,,)(op1, op2);
}
svbool_t test_svwhilegt_b64_u32(uint32_t op1, uint32_t op2)
{
// CHECK-LABEL: test_svwhilegt_b64_u32
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i32(i32 %op1, i32 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b64_u32'}}
return SVE_ACLE_FUNC(svwhilegt_b64,_u32,,)(op1, op2);
}
svbool_t test_svwhilegt_b8_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b8_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_s64'}}
return SVE_ACLE_FUNC(svwhilegt_b8,_s64,,)(op1, op2);
}
svbool_t test_svwhilegt_b16_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b16_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b16_s64'}}
return SVE_ACLE_FUNC(svwhilegt_b16,_s64,,)(op1, op2);
}
svbool_t test_svwhilegt_b32_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b32_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b32_s64'}}
return SVE_ACLE_FUNC(svwhilegt_b32,_s64,,)(op1, op2);
}
svbool_t test_svwhilegt_b64_s64(int64_t op1, int64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b64_s64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b64_s64'}}
return SVE_ACLE_FUNC(svwhilegt_b64,_s64,,)(op1, op2);
}
svbool_t test_svwhilegt_b8_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b8_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64 %op1, i64 %op2)
// CHECK: ret <vscale x 16 x i1> %[[INTRINSIC]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_u64'}}
return SVE_ACLE_FUNC(svwhilegt_b8,_u64,,)(op1, op2);
}
svbool_t test_svwhilegt_b16_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b16_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b16'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b16_u64'}}
return SVE_ACLE_FUNC(svwhilegt_b16,_u64,,)(op1, op2);
}
svbool_t test_svwhilegt_b32_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b32_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b32'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b32_u64'}}
return SVE_ACLE_FUNC(svwhilegt_b32,_u64,,)(op1, op2);
}
svbool_t test_svwhilegt_b64_u64(uint64_t op1, uint64_t op2)
{
// CHECK-LABEL: test_svwhilegt_b64_u64
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i64(i64 %op1, i64 %op2)
// CHECK: %[[CAST:.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %[[INTRINSIC]])
// CHECK: ret <vscale x 16 x i1> %[[CAST]]
// overload-warning@+2 {{implicit declaration of function 'svwhilegt_b64'}}
// expected-warning@+1 {{implicit declaration of function 'svwhilegt_b64_u64'}}
return SVE_ACLE_FUNC(svwhilegt_b64,_u64,,)(op1, op2);
}

clang/utils/TableGen/SveEmitter.cpp

Show First 20 Lines • Show All 514 Lines • ▼ Show 20 Lines case 'I':
Predicate = false; Predicate = false;
Float = false; Float = false;
ElementBitwidth = Bitwidth = 32; ElementBitwidth = Bitwidth = 32;
NumVectors = 0; NumVectors = 0;
Signed = true; Signed = true;
Immediate = true; Immediate = true;
PredicatePattern = true; PredicatePattern = true;
break; break;
case 'k':
Predicate = false;
Signed = true;
Float = false;
ElementBitwidth = Bitwidth = 32;
NumVectors = 0;
break;
case 'l': case 'l':
Predicate = false; Predicate = false;
Signed = true; Signed = true;
Float = false; Float = false;
ElementBitwidth = Bitwidth = 64; ElementBitwidth = Bitwidth = 64;
NumVectors = 0; NumVectors = 0;
break; break;
case 'm':
Predicate = false;
Signed = false;
Float = false;
ElementBitwidth = Bitwidth = 32;
NumVectors = 0;
break;
case 'n':
Predicate = false;
Signed = false;
Float = false;
ElementBitwidth = Bitwidth = 64;
NumVectors = 0;
break;
case 'S': case 'S':
Constant = true; Constant = true;
Pointer = true; Pointer = true;
ElementBitwidth = Bitwidth = 8; ElementBitwidth = Bitwidth = 8;
NumVectors = 0; NumVectors = 0;
Signed = true; Signed = true;
break; break;
case 'W': case 'W':
▲ Show 20 Lines • Show All 587 Lines • Show Last 20 Lines