PowerPCSPE: Stop libunwind from complaining about SPE registers

[jhibbits]

Summary

• Match SPE "DWARF" register numbers to GCC's instead of official DWARF documentation.
• Increase the register count to 148 from 112, even though the upper registers aren't saved (yet).

[compnerd]

Im surprised that no tests need changing here. Could you please add a clang/llvm test to validate that the generated information matches what libunwind will start looking for?

[jhibbits]

In D77433#1961097, @compnerd wrote:

Im surprised that no tests need changing here. Could you please add a clang/llvm test to validate that the generated information matches what libunwind will start looking for?

I'm looking for any existing tests for PowerPC that might do this for the GPRs and FPRs, but don't see any. Do you know of any tests already? Or tests for other archs I can model one on?

[MaskRay]

In D77433#1961097, @compnerd wrote:

Im surprised that no tests need changing here. Could you please add a clang/llvm test to validate that the generated information matches what libunwind will start looking for?

libunwind is really, really, poorly tested:(

[compnerd]

The tests that I was requesting were for clang/LLVM. Testing libunwind is challenging as it requires runtime tests, and that means that in order to test it effectively, you need each type of machine. I suppose that in theory, you could build a VM based on LLVM's JIT, cross-compile the library, binary translate the code and test it - but that seems incredibly fragile.

[jhibbits]

Turns out GCC generates 1200-range register values. This still needs work to avoid the error, but it means giving libunwind special knowledge of the SPE register set.

libunwind/include/__libunwind_config.h

 
 #if defined(__arm__) && !defined(__USING_SJLJ_EXCEPTIONS__) && \
     !defined(__ARM_DWARF_EH__)
 #define _LIBUNWIND_ARM_EHABI
 #endif
 
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86       8
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64    32
-#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC       112
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC       148
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64     116
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64     95
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM       287
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K      32
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS      65
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC     31
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     64
 

libunwind/include/libunwind.h

enum {
   UNW_X86_64_XMM13 = 30,
   UNW_X86_64_XMM14 = 31,
   UNW_X86_64_XMM15 = 32,
 };
 
 
 // 32-bit ppc register numbers
 enum {
   UNW_PPC_R0  = 0,
   UNW_PPC_R1  = 1,
   UNW_PPC_R2  = 2,
   UNW_PPC_R3  = 3,
   UNW_PPC_R4  = 4,
   UNW_PPC_R5  = 5,
   UNW_PPC_R6  = 6,
   UNW_PPC_R7  = 7,
   UNW_PPC_R8  = 8,
enum {
   UNW_PPC_R24 = 24,
   UNW_PPC_R25 = 25,
   UNW_PPC_R26 = 26,
   UNW_PPC_R27 = 27,
   UNW_PPC_R28 = 28,
   UNW_PPC_R29 = 29,
   UNW_PPC_R30 = 30,
   UNW_PPC_R31 = 31,
   UNW_PPC_F0  = 32,
   UNW_PPC_F1  = 33,
   UNW_PPC_F2  = 34,
   UNW_PPC_F3  = 35,
   UNW_PPC_F4  = 36,
   UNW_PPC_F5  = 37,
   UNW_PPC_F6  = 38,
   UNW_PPC_F7  = 39,
   UNW_PPC_F8  = 40,
enum {
   UNW_PPC_F24 = 56,
   UNW_PPC_F25 = 57,
   UNW_PPC_F26 = 58,
   UNW_PPC_F27 = 59,
   UNW_PPC_F28 = 60,
   UNW_PPC_F29 = 61,
   UNW_PPC_F30 = 62,
   UNW_PPC_F31 = 63,
   UNW_PPC_MQ  = 64,
   UNW_PPC_LR  = 65,
   UNW_PPC_CTR = 66,
   UNW_PPC_AP  = 67,
   UNW_PPC_CR0 = 68,
   UNW_PPC_CR1 = 69,
   UNW_PPC_CR2 = 70,
   UNW_PPC_CR3 = 71,
   UNW_PPC_CR4 = 72,
   UNW_PPC_CR5 = 73,
   UNW_PPC_CR6 = 74,
   UNW_PPC_CR7 = 75,
   UNW_PPC_XER = 76,
   UNW_PPC_V0  = 77,
   UNW_PPC_V1  = 78,
   UNW_PPC_V2  = 79,
   UNW_PPC_V3  = 80,
   UNW_PPC_V4  = 81,
   UNW_PPC_V5  = 82,
   UNW_PPC_V6  = 83,
   UNW_PPC_V7  = 84,
   UNW_PPC_V8  = 85,
enum {
   UNW_PPC_V24 = 101,
   UNW_PPC_V25 = 102,
   UNW_PPC_V26 = 103,
   UNW_PPC_V27 = 104,
   UNW_PPC_V28 = 105,
   UNW_PPC_V29 = 106,
   UNW_PPC_V30 = 107,
   UNW_PPC_V31 = 108,
   UNW_PPC_VRSAVE  = 109,
   UNW_PPC_VSCR    = 110,
   UNW_PPC_SPE_ACC = 111,
-  UNW_PPC_SPEFSCR = 112
+  UNW_PPC_SPEFSCR = 112,
+  UNW_PPC_RH0 = 117,
+  UNW_PPC_RH1 = 118,
+  UNW_PPC_RH2 = 119,
+  UNW_PPC_RH3 = 120,
+  UNW_PPC_RH4 = 121,
+  UNW_PPC_RH5 = 122,
+  UNW_PPC_RH6 = 123,
+  UNW_PPC_RH7 = 124,
+  UNW_PPC_RH8 = 125,
+  UNW_PPC_RH9 = 126,
+  UNW_PPC_RH10 = 117,
+  UNW_PPC_RH11 = 128,
+  UNW_PPC_RH12 = 129,
+  UNW_PPC_RH13 = 130,
+  UNW_PPC_RH14 = 131,
+  UNW_PPC_RH15 = 132,
+  UNW_PPC_RH16 = 133,
+  UNW_PPC_RH17 = 134,
+  UNW_PPC_RH18 = 135,
+  UNW_PPC_RH19 = 136,
+  UNW_PPC_RH20 = 137,
+  UNW_PPC_RH21 = 138,
+  UNW_PPC_RH22 = 139,
+  UNW_PPC_RH23 = 140,
+  UNW_PPC_RH24 = 141,
+  UNW_PPC_RH25 = 142,
+  UNW_PPC_RH26 = 143,
+  UNW_PPC_RH27 = 144,
+  UNW_PPC_RH28 = 145,
+  UNW_PPC_RH29 = 146,
+  UNW_PPC_RH30 = 147,
+  UNW_PPC_RH31 = 148
 };
 
 // 64-bit ppc register numbers
 enum {
   UNW_PPC64_R0      = 0,
   UNW_PPC64_R1      = 1,
   UNW_PPC64_R2      = 2,
   UNW_PPC64_R3      = 3,

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 foreach Index = 0-31 in {
   def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
                     DwarfRegNum<[Index, -2]>;
 }
 
 // SPE registers
 foreach Index = 0-31 in {
   def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>,
-                    DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;
+                    DwarfRegNum<[!add(Index, 117), !add(Index, 117)]>;
 }
 
 // Floating-point registers
 foreach Index = 0-31 in {
   def F#Index : FPR<Index, "f"#Index>,
                 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
 }