[ARM] Fix qdadd operand order

[dmgreen]

Summary

qdadd is defined as sat(Rm + sat(2*Rn)). We had the Rm and Rn switched the wrong way around.

[samparker]

Cheers!

llvm/lib/Target/ARM/ARMInstrInfo.td

 // Saturating add/subtract
 let hasSideEffects = 1 in {
 def QADD8   : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>;
 def QADD16  : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>;
 def QSUB16  : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>;
 def QSUB8   : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>;
 
 def QDADD   : AAIRevOpr<0b00010100, 0b00000101, "qdadd",
-              [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm,
-                                                             GPRnopc:$Rm),
-                                  GPRnopc:$Rn))]>;
+              [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm,
+                                  (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
 def QDSUB   : AAIRevOpr<0b00010110, 0b00000101, "qdsub",
               [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm,
                                   (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
 def QSUB    : AAIRevOpr<0b00010010, 0b00000101, "qsub",
               [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
 let DecoderMethod = "DecodeQADDInstruction" in
   def QADD    : AAIRevOpr<0b00010000, 0b00000101, "qadd",
                 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
 }
 
 def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b),
                  (QADD GPR:$a, GPR:$b)>;
 def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b),
                  (QSUB GPR:$a, GPR:$b)>;
-def : ARMV5TEPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
+def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
                  (QDADD rGPR:$Rm, rGPR:$Rn)>;
 def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
                  (QDSUB rGPR:$Rm, rGPR:$Rn)>;
 def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
                (QADD8 rGPR:$Rm, rGPR:$Rn)>;
 def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
                (QSUB8 rGPR:$Rm, rGPR:$Rn)>;
 def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),

llvm/lib/Target/ARM/ARMInstrThumb2.td

 def t2QSUB    : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">;
 def t2QDADD   : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;
 def t2QDSUB   : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;
 
 def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, rGPR:$Rn),
                    (t2QADD rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn),
                    (t2QSUB rGPR:$Rm, rGPR:$Rn)>;
-def : Thumb2DSPPat<(int_arm_qadd(int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
+def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),
                    (t2QDADD rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),
                    (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
 
 def : Thumb2DSPPat<(saddsat rGPR:$Rm, rGPR:$Rn),
                    (t2QADD rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(ssubsat rGPR:$Rm, rGPR:$Rn),
                    (t2QSUB rGPR:$Rm, rGPR:$Rn)>;
-def : Thumb2DSPPat<(saddsat(saddsat rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
+def : Thumb2DSPPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
                    (t2QDADD rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
                    (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
                    (t2QADD8 rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
                    (t2QSUB8 rGPR:$Rm, rGPR:$Rn)>;
 def : Thumb2DSPPat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),

llvm/test/CodeGen/ARM/acle-intrinsics-v5.ll

 ; CHECK-LABEL: qsub
 ; CHECK: qsub r0, r0, r1
   %tmp = call i32 @llvm.arm.qsub(i32 %a, i32 %b)
   ret i32 %tmp
 }
 
 define i32 @qdadd(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: qdadd
-; CHECK: qdadd r0, r0, r1
+; CHECK: qdadd r0, r1, r0
   %dbl = call i32 @llvm.arm.qadd(i32 %a, i32 %a)
   %add = call i32 @llvm.arm.qadd(i32 %dbl, i32 %b)
   ret i32 %add
 }
 
 define i32 @qdsub(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: qdsub
 ; CHECK: qdsub r0, r0, r1

llvm/test/CodeGen/ARM/qdadd.ll

 ; CHECK-T2NODSP-NEXT:    cmp r0, r3
 ; CHECK-T2NODSP-NEXT:    it vc
 ; CHECK-T2NODSP-NEXT:    movvc r2, r0
 ; CHECK-T2NODSP-NEXT:    mov r0, r2
 ; CHECK-T2NODSP-NEXT:    pop {r7, pc}
 ;
 ; CHECK-T2DSP-LABEL: qdadd:
 ; CHECK-T2DSP:       @ %bb.0:
-; CHECK-T2DSP-NEXT:    qdadd r0, r0, r1
+; CHECK-T2DSP-NEXT:    qdadd r0, r1, r0
 ; CHECK-T2DSP-NEXT:    bx lr
 ;
 ; CHECK-ARM-LABEL: qdadd:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM-NEXT:    qdadd r0, r0, r1
+; CHECK-ARM-NEXT:    qdadd r0, r1, r0
 ; CHECK-ARM-NEXT:    bx lr
   %z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
   %tmp = call i32 @llvm.sadd.sat.i32(i32 %z, i32 %y)
   ret i32 %tmp
 }
 
 define i32 @qdadd_c(i32 %x, i32 %y) nounwind {
 ; CHECK-T2NODSP-LABEL: qdadd_c:

 ; CHECK-T2NODSP-NEXT:    cmp r0, r1
 ; CHECK-T2NODSP-NEXT:    it vc
 ; CHECK-T2NODSP-NEXT:    movvc r2, r0
 ; CHECK-T2NODSP-NEXT:    mov r0, r2
 ; CHECK-T2NODSP-NEXT:    pop {r7, pc}
 ;
 ; CHECK-T2DSP-LABEL: qdadd_c:
 ; CHECK-T2DSP:       @ %bb.0:
-; CHECK-T2DSP-NEXT:    qdadd r0, r0, r1
+; CHECK-T2DSP-NEXT:    qdadd r0, r1, r0
 ; CHECK-T2DSP-NEXT:    bx lr
 ;
 ; CHECK-ARM-LABEL: qdadd_c:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM-NEXT:    qdadd r0, r0, r1
+; CHECK-ARM-NEXT:    qdadd r0, r1, r0
 ; CHECK-ARM-NEXT:    bx lr
   %z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
   %tmp = call i32 @llvm.sadd.sat.i32(i32 %y, i32 %z)
   ret i32 %tmp
 }
 
 define i32 @qdsub(i32 %x, i32 %y) nounwind {
 ; CHECK-T2NODSP-LABEL: qdsub: