[X86][SSE] Handle basic inversion of PTEST/TESTP operands (PR38522)

[RKSimon]

Summary

PTEST/TESTP sets EFLAGS as:
TESTZ: ZF = (Op0 & Op1) == 0
TESTC: CF = (~Op0 & Op1) == 0
TESTNZC: ZF == 0 && CF == 0

If we are inverting the 0'th operand of a PTEST/TESTP instruction we can adjust the comparisons to correct handle the inversion implicitly.

Additionally, for "TESTZ" (ZF) cases, the allones case, PTEST(X,-1) can be simplified to PTEST(X,X).

We can expand this for the TEST(X,~Y) pattern and also handle KTEST/KORTEST as well but I wanted to get some initial feedback first.

[RKSimon]

sorry, git stash screwed up - fixed version shortly.

[RKSimon]

fixed merge

[craig.topper]

This feels subject to DAG combine ordering not folding the cmov+setcc before this combine gets a chance to run. Would this be simpler if we just did it at the intrinsic lowering stage?

[RKSimon]

In D76984#1948186, @craig.topper wrote:

This feels subject to DAG combine ordering not folding the cmov+setcc before this combine gets a chance to run. Would this be simpler if we just did it at the intrinsic lowering stage?

The problem we're going to hit is that most of the xor(X,-1) inversions cases are coming from comparison lowering - PR38522 in particular hits this. What about if I extend the CondCode cases handled? I was thinking about adding a thorough 'X86::GetComplementCondCode' helper, and possibly one that checks which flag bits are read.

[craig.topper]

Is this something we can handle in combineSetCCEFLAGS?

[RKSimon]

Move combine inside combineSetCCEFLAGS

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

39858

Can we also handle COND_BE? Not sure if its possible for COND_A to get inverted before we get here

[RKSimon]

Rebased tests and added COND_BE testnzc case.

[RKSimon]

Tweaked new ptestnzc_256_invert0_commute test for X86::COND_BE case

[craig.topper]

LGTM

llvm/lib/Target/X86/X86ISelLowering.cpp

if (isAllOnesConstant(EFLAGS.getOperand(1))) {
           return CarryOp1;
       }
     }
   }
 
   return SDValue();
 }
 
+/// If we are inverting an PTEST/TESTP operand, attempt to adjust the CC
+/// to avoid the inversion.
+static SDValue combinePTESTCC(SDValue EFLAGS, X86::CondCode &CC,
+                              SelectionDAG &DAG) {
+  // TODO: Handle X86ISD::KTEST/X86ISD::KORTEST.
+  if (EFLAGS.getOpcode() != X86ISD::PTEST &&
+      EFLAGS.getOpcode() != X86ISD::TESTP)
+    return SDValue();
+
+  // PTEST/TESTP sets EFLAGS as:
+  // TESTZ: ZF = (Op0 & Op1) == 0
+  // TESTC: CF = (~Op0 & Op1) == 0
+  // TESTNZC: ZF == 0 && CF == 0
+  EVT VT = EFLAGS.getValueType();
+  SDValue Op0 = EFLAGS.getOperand(0);
+  SDValue Op1 = EFLAGS.getOperand(1);
+  EVT OpVT = Op0.getValueType();
+
+  // TEST*(~X,Y) == TEST*(X,Y)
+  if (SDValue NotOp0 = IsNOT(Op0, DAG)) {
+    X86::CondCode InvCC;
+    switch (CC) {
+    case X86::COND_B:
+      // testc -> testz.
+      InvCC = X86::COND_E;
+      break;
+    case X86::COND_AE:
+      // !testc -> !testz.
+      InvCC = X86::COND_NE;
+      break;
+    case X86::COND_E:
+      // testz -> testc.
+      InvCC = X86::COND_B;
+      break;
+    case X86::COND_NE:
+      // !testz -> !testc.
+      InvCC = X86::COND_AE;
+      break;
+    case X86::COND_A:
+    case X86::COND_BE:
+      // testnzc -> testnzc (no change).
+      InvCC = CC;
+      break;
+    default:
+      InvCC = X86::COND_INVALID;
+      break;
+    }
+
+    if (InvCC != X86::COND_INVALID) {
+      CC = InvCC;
+      return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT,
+                         DAG.getBitcast(OpVT, NotOp0), Op1);
+    }
+  }
+
+  // TODO: TESTZ(X,~Y) == TESTC(Y,X)
+
+  // TESTZ(X,-1) == TESTZ(X,X)
+  // TESTZ(-1,X) == TESTZ(X,X)
+  if (CC == X86::COND_E || CC == X86::COND_NE) {
+    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
+      return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, Op1, Op1);
+    if (ISD::isBuildVectorAllOnes(Op1.getNode()))
+      return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, Op0, Op0);
+  }
+
+  return SDValue();
+}
+
 /// Optimize an EFLAGS definition used according to the condition code \p CC
 /// into a simpler EFLAGS value, potentially returning a new \p CC and replacing
 /// uses of chain values.
 static SDValue combineSetCCEFLAGS(SDValue EFLAGS, X86::CondCode &CC,
                                   SelectionDAG &DAG,
                                   const X86Subtarget &Subtarget) {
   if (CC == X86::COND_B)
     if (SDValue Flags = combineCarryThroughADD(EFLAGS, DAG))
       return Flags;
 
   if (SDValue R = checkBoolTestSetCCCombine(EFLAGS, CC))
     return R;
+
+  if (SDValue R = combinePTESTCC(EFLAGS, CC, DAG))
+    return R;
+
   return combineSetCCAtomicArith(EFLAGS, CC, DAG, Subtarget);
 }
 
 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
 static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
                            TargetLowering::DAGCombinerInfo &DCI,
                            const X86Subtarget &Subtarget) {
   SDLoc DL(N);

llvm/test/CodeGen/X86/combine-ptest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
 ;
 ; testz(~X,Y) -> testc(X,Y)
 ;
 
 define i32 @ptestz_128_invert0(<2 x i64> %c, <2 x i64> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vptest %xmm1, %xmm0
-; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    cmovael %esi, %eax
 ; CHECK-NEXT:    retq
   %t1 = xor <2 x i64> %c, <i64 -1, i64 -1>
   %t2 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> %d)
   %t3 = icmp ne i32 %t2, 0
   %t4 = select i1 %t3, i32 %a, i32 %b
   ret i32 %t4
 }
 
 define i32 @ptestz_256_invert0(<4 x i64> %c, <4 x i64> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vptest %ymm1, %ymm0
-; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    cmovael %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t1 = xor <4 x i64> %c, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %t1, <4 x i64> %d)
   %t3 = icmp ne i32 %t2, 0
   %t4 = select i1 %t3, i32 %a, i32 %b
   ret i32 %t4
 }

 ;
 ; testc(~X,Y) -> testz(X,Y)
 ;
 
 define i32 @ptestc_128_invert0(<2 x i64> %c, <2 x i64> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestc_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vptest %xmm1, %xmm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    retq
   %t1 = xor <2 x i64> %c, <i64 -1, i64 -1>
   %t2 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %d)
   %t3 = icmp ne i32 %t2, 0
   %t4 = select i1 %t3, i32 %a, i32 %b
   ret i32 %t4
 }
 
 define i32 @ptestc_256_invert0(<4 x i64> %c, <4 x i64> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestc_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vptest %ymm1, %ymm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t1 = xor <4 x i64> %c, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %t1, <4 x i64> %d)
   %t3 = icmp ne i32 %t2, 0
   %t4 = select i1 %t3, i32 %a, i32 %b
   ret i32 %t4
 }
 
 ;
 ; testnzc(~X,Y) -> testnzc(X,Y)
 ;
 
 define i32 @ptestnzc_128_invert0(<2 x i64> %c, <2 x i64> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestnzc_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vptest %xmm1, %xmm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    retq
   %t1 = xor <2 x i64> %c, <i64 -1, i64 -1>
   %t2 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %d)
   %t3 = icmp ne i32 %t2, 0
   %t4 = select i1 %t3, i32 %a, i32 %b
   ret i32 %t4
 }
 
 define i32 @ptestnzc_256_invert0(<4 x i64> %c, <4 x i64> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestnzc_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vptest %ymm1, %ymm0
 ; CHECK-NEXT:    cmovbel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t1 = xor <4 x i64> %c, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %t1, <4 x i64> %d)
   %t3 = icmp ne i32 %t2, 0
   %t4 = select i1 %t3, i32 %a, i32 %b
   ret i32 %t4
 }
 
+define i32 @ptestnzc_256_invert0_commute(<4 x i64> %c, <4 x i64> %d, i32 %a, i32 %b) {
+; CHECK-LABEL: ptestnzc_256_invert0_commute:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vptest %ymm1, %ymm0
+; CHECK-NEXT:    cmoval %esi, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t1 = xor <4 x i64> %c, <i64 -1, i64 -1, i64 -1, i64 -1>
+  %t2 = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %t1, <4 x i64> %d)
+  %t3 = icmp eq i32 %t2, 0
+  %t4 = select i1 %t3, i32 %a, i32 %b
+  ret i32 %t4
+}
+
 ;
 ; testz(-1,X) -> testz(X,X)
 ;
 
 define i32 @ptestz_128_allones0(<2 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_128_allones0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT:    vptest %xmm0, %xmm1
+; CHECK-NEXT:    vptest %xmm0, %xmm0
 ; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    retq
   %t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> <i64 -1, i64 -1>, <2 x i64> %c)
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 %a, i32 %b
   ret i32 %t3
 }
 
 define i32 @ptestz_256_allones0(<4 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_256_allones0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT:    vcmptrueps %ymm1, %ymm1, %ymm1
-; CHECK-NEXT:    vptest %ymm0, %ymm1
+; CHECK-NEXT:    vptest %ymm0, %ymm0
 ; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t1 = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, <4 x i64> %c)
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 %a, i32 %b
   ret i32 %t3
 }
 
 ;
 ; testz(X,-1) -> testz(X,X)
 ;
 
 define i32 @ptestz_128_allones1(<2 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_128_allones1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT:    vptest %xmm1, %xmm0
+; CHECK-NEXT:    vptest %xmm0, %xmm0
 ; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    retq
   %t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> <i64 -1, i64 -1>)
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 %a, i32 %b
   ret i32 %t3
 }
 
 define i32 @ptestz_256_allones1(<4 x i64> %c, i32 %a, i32 %b) {
 ; CHECK-LABEL: ptestz_256_allones1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm1, %xmm1, %xmm1
-; CHECK-NEXT:    vcmptrueps %ymm1, %ymm1, %ymm1
-; CHECK-NEXT:    vptest %ymm1, %ymm0
+; CHECK-NEXT:    vptest %ymm0, %ymm0
 ; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t1 = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %c, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>)
   %t2 = icmp ne i32 %t1, 0
   %t3 = select i1 %t2, i32 %a, i32 %b
   ret i32 %t3
 }
 
 define zeroext i1 @PR38522(<16 x i8>* %x, <16 x i8>* %y) {
 ; CHECK-LABEL: PR38522:
 ; CHECK:       # %bb.0: # %start
 ; CHECK-NEXT:    vmovdqa (%rdi), %xmm0
 ; CHECK-NEXT:    vpcmpgtb (%rsi), %xmm0, %xmm0
-; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT:    vpxor %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vptest %xmm1, %xmm0
-; CHECK-NEXT:    setb %al
+; CHECK-NEXT:    vptest %xmm0, %xmm0
+; CHECK-NEXT:    sete %al
 ; CHECK-NEXT:    retq
 start:
   %0 = load <16 x i8>, <16 x i8>* %x, align 16
   %1 = load <16 x i8>, <16 x i8>* %y, align 16
   %2 = icmp sle <16 x i8> %0, %1
   %3 = sext <16 x i1> %2 to <16 x i8>
   %4 = bitcast <16 x i8> %3 to <2 x i64>
   %5 = tail call i32 @llvm.x86.sse41.ptestc(<2 x i64> %4, <2 x i64> <i64 -1, i64 -1>)

llvm/test/CodeGen/X86/combine-testpd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
 ;
 ; testz(~X,Y) -> testc(X,Y)
 ;
 
 define i32 @testpdz_128_invert0(<2 x double> %c, <2 x double> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdz_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vtestpd %xmm1, %xmm0
-; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    cmovael %esi, %eax
 ; CHECK-NEXT:    retq
   %t0 = bitcast <2 x double> %c to <2 x i64>
   %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
   %t2 = bitcast <2 x i64> %t1 to <2 x double>
   %t3 = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %t2, <2 x double> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 define i32 @testpdz_256_invert0(<4 x double> %c, <4 x double> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdz_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vtestpd %ymm1, %ymm0
-; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    cmovael %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t0 = bitcast <4 x double> %c to <4 x i64>
   %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = bitcast <4 x i64> %t1 to <4 x double>
   %t3 = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %t2, <4 x double> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b

 ;
 ; testc(~X,Y) -> testz(X,Y)
 ;
 
 define i32 @testpdc_128_invert0(<2 x double> %c, <2 x double> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdc_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vtestpd %xmm1, %xmm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    retq
   %t0 = bitcast <2 x double> %c to <2 x i64>
   %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
   %t2 = bitcast <2 x i64> %t1 to <2 x double>
   %t3 = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %t2, <2 x double> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 define i32 @testpdc_256_invert0(<4 x double> %c, <4 x double> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdc_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vtestpd %ymm1, %ymm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t0 = bitcast <4 x double> %c to <4 x i64>
   %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = bitcast <4 x i64> %t1 to <4 x double>
   %t3 = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %t2, <4 x double> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 ;
 ; testnzc(~X,Y) -> testnzc(X,Y)
 ;
 
 define i32 @testpdnzc_128_invert0(<2 x double> %c, <2 x double> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdnzc_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vtestpd %xmm1, %xmm0
 ; CHECK-NEXT:    cmovbel %esi, %eax
 ; CHECK-NEXT:    retq
   %t0 = bitcast <2 x double> %c to <2 x i64>
   %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
   %t2 = bitcast <2 x i64> %t1 to <2 x double>
   %t3 = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %t2, <2 x double> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 define i32 @testpdnzc_256_invert0(<4 x double> %c, <4 x double> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpdnzc_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vtestpd %ymm1, %ymm0
 ; CHECK-NEXT:    cmovbel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t0 = bitcast <4 x double> %c to <4 x i64>
   %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = bitcast <4 x i64> %t1 to <4 x double>
   %t3 = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %t2, <4 x double> %d)

llvm/test/CodeGen/X86/combine-testps.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
 
 ;
 ; testz(~X,Y) -> testc(X,Y)
 ;
 
 define i32 @testpsz_128_invert0(<4 x float> %c, <4 x float> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsz_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vtestps %xmm1, %xmm0
-; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    cmovael %esi, %eax
 ; CHECK-NEXT:    retq
   %t0 = bitcast <4 x float> %c to <2 x i64>
   %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
   %t2 = bitcast <2 x i64> %t1 to <4 x float>
   %t3 = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %t2, <4 x float> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 define i32 @testpsz_256_invert0(<8 x float> %c, <8 x float> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsz_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vtestps %ymm1, %ymm0
-; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    cmovael %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t0 = bitcast <8 x float> %c to <4 x i64>
   %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = bitcast <4 x i64> %t1 to <8 x float>
   %t3 = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %t2, <8 x float> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b

 ;
 ; testc(~X,Y) -> testz(X,Y)
 ;
 
 define i32 @testpsc_128_invert0(<4 x float> %c, <4 x float> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsc_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vtestps %xmm1, %xmm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    retq
   %t0 = bitcast <4 x float> %c to <2 x i64>
   %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
   %t2 = bitcast <2 x i64> %t1 to <4 x float>
   %t3 = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %t2, <4 x float> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 define i32 @testpsc_256_invert0(<8 x float> %c, <8 x float> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsc_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vtestps %ymm1, %ymm0
-; CHECK-NEXT:    cmovael %esi, %eax
+; CHECK-NEXT:    cmovnel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t0 = bitcast <8 x float> %c to <4 x i64>
   %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = bitcast <4 x i64> %t1 to <8 x float>
   %t3 = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %t2, <8 x float> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 ;
 ; testnzc(~X,Y) -> testnzc(X,Y)
 ;
 
 define i32 @testpsnzc_128_invert0(<4 x float> %c, <4 x float> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsnzc_128_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vpcmpeqd %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vpxor %xmm2, %xmm0, %xmm0
 ; CHECK-NEXT:    vtestps %xmm1, %xmm0
 ; CHECK-NEXT:    cmovbel %esi, %eax
 ; CHECK-NEXT:    retq
   %t0 = bitcast <4 x float> %c to <2 x i64>
   %t1 = xor <2 x i64> %t0, <i64 -1, i64 -1>
   %t2 = bitcast <2 x i64> %t1 to <4 x float>
   %t3 = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %t2, <4 x float> %d)
   %t4 = icmp ne i32 %t3, 0
   %t5 = select i1 %t4, i32 %a, i32 %b
   ret i32 %t5
 }
 
 define i32 @testpsnzc_256_invert0(<8 x float> %c, <8 x float> %d, i32 %a, i32 %b) {
 ; CHECK-LABEL: testpsnzc_256_invert0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
-; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; CHECK-NEXT:    vcmptrueps %ymm2, %ymm2, %ymm2
-; CHECK-NEXT:    vxorps %ymm2, %ymm0, %ymm0
 ; CHECK-NEXT:    vtestps %ymm1, %ymm0
 ; CHECK-NEXT:    cmovbel %esi, %eax
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %t0 = bitcast <8 x float> %c to <4 x i64>
   %t1 = xor <4 x i64> %t0, <i64 -1, i64 -1, i64 -1, i64 -1>
   %t2 = bitcast <4 x i64> %t1 to <8 x float>
   %t3 = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %t2, <8 x float> %d)