[VE] Change name of enum to CondCode

[kaz7]

Summary

Change enum name for condition codes from CondCodes to CondCode.

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

void VEInstPrinter::printMemASOperand(const MCInst *MI, int opNum,
   O << "(";
   printOperand(MI, opNum, STI, O);
   O << ")";
 }
 
 void VEInstPrinter::printCCOperand(const MCInst *MI, int opNum,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   int CC = (int)MI->getOperand(opNum).getImm();
-  O << VECondCodeToString((VECC::CondCodes)CC);
+  O << VECondCodeToString((VECC::CondCode)CC);
 }

llvm/lib/Target/VE/VE.h

 void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                  AsmPrinter &AP);
 } // namespace llvm
 
 namespace llvm {
 // Enums corresponding to VE condition codes, both icc's and fcc's.  These
 // values must be kept in sync with the ones in the .td file.
 namespace VECC {
-enum CondCodes {
+enum CondCode {
   // Integer comparison
   CC_IG =  0,  // Greater
   CC_IL =  1,  // Less
   CC_INE = 2, // Not Equal
   CC_IEQ = 3, // Equal
   CC_IGE = 4, // Greater or Equal
   CC_ILE = 5, // Less or Equal
 
   // Floating point comparison
   CC_AF =     0 + 6, // Never
   CC_G =      1 + 6, // Greater
   CC_L =      2 + 6, // Less
   CC_NE =     3 + 6, // Not Equal
   CC_EQ =     4 + 6, // Equal
   CC_GE =     5 + 6, // Greater or Equal
   CC_LE =     6 + 6, // Less or Equal
   CC_NUM =    7 + 6, // Number
   CC_NAN =    8 + 6, // NaN
   CC_GNAN =   9 + 6, // Greater or NaN
   CC_LNAN =  10 + 6, // Less or NaN
   CC_NENAN = 11 + 6, // Not Equal or NaN
   CC_EQNAN = 12 + 6, // Equal or NaN
   CC_GENAN = 13 + 6, // Greater or Equal or NaN
   CC_LENAN = 14 + 6, // Less or Equal or NaN
   CC_AT =    15 + 6, // Always
 };
 }
 
-inline static const char *VECondCodeToString(VECC::CondCodes CC) {
+inline static const char *VECondCodeToString(VECC::CondCode CC) {
   switch (CC) {
   case VECC::CC_IG:    return "gt";
   case VECC::CC_IL:    return "lt";
   case VECC::CC_INE:   return "ne";
   case VECC::CC_IEQ:   return "eq";
   case VECC::CC_IGE:   return "ge";
   case VECC::CC_ILE:   return "le";
   case VECC::CC_AF:    return "af";

llvm/lib/Target/VE/VEInstrInfo.cpp

 // Pin the vtable to this file.
 void VEInstrInfo::anchor() {}
 
 VEInstrInfo::VEInstrInfo(VESubtarget &ST)
     : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
 
 static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); }
 
-static VECC::CondCodes GetOppositeBranchCondition(VECC::CondCodes CC) {
+static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) {
   switch(CC) {
   case VECC::CC_IG:     return VECC::CC_ILE;
   case VECC::CC_IL:     return VECC::CC_IGE;
   case VECC::CC_INE:    return VECC::CC_IEQ;
   case VECC::CC_IEQ:    return VECC::CC_INE;
   case VECC::CC_IGE:    return VECC::CC_IL;
   case VECC::CC_ILE:    return VECC::CC_IG;
   case VECC::CC_AF:     return VECC::CC_AT;
while (I != MBB.begin()) {
     I = MBB.end();
     ++Count;
   }
   return Count;
 }
 
 bool VEInstrInfo::reverseBranchCondition(
     SmallVectorImpl<MachineOperand> &Cond) const {
-  VECC::CondCodes CC = static_cast<VECC::CondCodes>(Cond[0].getImm());
+  VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm());
   Cond[0].setImm(GetOppositeBranchCondition(CC));
   return false;
 }
 
 static bool IsAliasOfSX(Register Reg) {
   return VE::I8RegClass.contains(Reg) || VE::I16RegClass.contains(Reg) ||
          VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
          VE::F32RegClass.contains(Reg);

llvm/lib/Target/VE/VEInstrInfo.td

 
 def HI32 : SDNodeXForm<imm, [{
   // Transformation function: shift the immediate value down into the low bits.
   return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
                                    SDLoc(N), MVT::i32);
 }]>;
 
 def icond2cc : SDNodeXForm<cond, [{
-  VECC::CondCodes cc;
+  VECC::CondCode cc;
   switch (N->get()) {
   default:          llvm_unreachable("Unknown integer condition code!");
   case ISD::SETEQ:  cc = VECC::CC_IEQ; break;
   case ISD::SETNE:  cc = VECC::CC_INE; break;
   case ISD::SETLT:  cc = VECC::CC_IL;  break;
   case ISD::SETGT:  cc = VECC::CC_IG;  break;
   case ISD::SETLE:  cc = VECC::CC_ILE; break;
   case ISD::SETGE:  cc = VECC::CC_IGE; break;
   case ISD::SETULT: cc = VECC::CC_IL;  break;
   case ISD::SETULE: cc = VECC::CC_ILE; break;
   case ISD::SETUGT: cc = VECC::CC_IG;  break;
   case ISD::SETUGE: cc = VECC::CC_IGE; break;
   }
   return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
 }]>;
 
 def fcond2cc : SDNodeXForm<cond, [{
-  VECC::CondCodes cc;
+  VECC::CondCode cc;
   switch (N->get()) {
   default:          llvm_unreachable("Unknown float condition code!");
   case ISD::SETFALSE: cc = VECC::CC_AF;    break;
   case ISD::SETEQ:
   case ISD::SETOEQ:   cc = VECC::CC_EQ;    break;
   case ISD::SETNE:
   case ISD::SETONE:   cc = VECC::CC_NE;    break;
   case ISD::SETLT: