[ARM][MVE] Add HorizontalReduction flag

[samparker]

Summary

Add a target flag for instructions that reduce into one, or more, scalar reg(s), including variants of:

• VADDV
• VABAV
• VMINV/VMAXV
• VMLADAV

[SjoerdMeijer]

LGTM

llvm/unittests/Target/ARM/MachineInstrTest.cpp

20

I haven't checked this list carefully in the ARMARM, but looks right and is safe anyway.

llvm/lib/Target/ARM/ARMInstrFormats.td

class InstTemplate<AddrMode am, int sz, IndexMode im,
   bit canXformTo16Bit = 0;
   // The instruction is a 16-bit flag setting Thumb instruction. Used
   // by the parser to determine whether to require the 'S' suffix on the
   // mnemonic (when not in an IT block) or preclude it (when in an IT block).
   bit thumbArithFlagSetting = 0;
 
   bit validForTailPredication = 0;
   bit retainsPreviousHalfElement = 0;
+  bit horizontalReduction = 0;
 
   // If this is a pseudo instruction, mark it isCodeGenOnly.
   let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
 
   // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
   let TSFlags{4-0}   = AM.Value;
   let TSFlags{6-5}   = IndexModeBits;
   let TSFlags{12-7} = Form;
   let TSFlags{13}    = isUnaryDataProc;
   let TSFlags{14}    = canXformTo16Bit;
   let TSFlags{18-15} = D.Value;
   let TSFlags{19}    = thumbArithFlagSetting;
   let TSFlags{20}    = validForTailPredication;
   let TSFlags{21}    = retainsPreviousHalfElement;
+  let TSFlags{22}    = horizontalReduction;
 
   let Constraints = cstr;
   let Itinerary = itin;
 }
 
 class Encoding {
   field bits<32> Inst;
   // Mask of bits that cause an encoding to be UNPREDICTABLE.

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VABAV<string suffix, bit U, bits<2> size>
   let Inst{16} = 0b0;
   let Inst{15-12} = Rda{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+  let horizontalReduction = 1;
 }
 
 multiclass MVE_VABAV_m<MVEVectorVTInfo VTI> {
   def "" : MVE_VABAV<VTI.Suffix, VTI.Unsigned, VTI.Size>;
   defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     def : Pat<(i32 (int_arm_mve_vabav
class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
   let Inst{19-18} = size{1-0};
   let Inst{17-16} = 0b01;
   let Inst{15-13} = Rda{3-1};
   let Inst{12} = 0b0;
   let Inst{8-6} = 0b100;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+  let horizontalReduction = 1;
 }
 
 def ARMVADDVs       : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
 def ARMVADDVu       : SDNode<"ARMISD::VADDVu", SDTVecReduce>;
 
 multiclass MVE_VADDV_A<MVEVectorVTInfo VTI> {
   def acc    : MVE_VADDV<"vaddva", VTI.Suffix,
                          (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
   let Inst{19-18} = 0b10;
   let Inst{17-16} = 0b01;
   let Inst{15-13} = RdaLo{3-1};
   let Inst{12} = 0b0;
   let Inst{8-6} = 0b100;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+  let horizontalReduction = 1;
 }
 
 def SDTVecReduceL : SDTypeProfile<2, 1, [    // VADDLV
   SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>
 ]>;
 def SDTVecReduceLA : SDTypeProfile<2, 3, [    // VADDLVA
   SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>,
   SDTCisVec<4>
class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
   let Inst{17} = bit_17;
   let Inst{16} = 0b0;
   let Inst{15-12} = RdaDest{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+  let horizontalReduction = 1;
 
   let Predicates = [HasMVEFloat];
 }
 
 multiclass MVE_VMINMAXNMV_p<string iname, bit notAbs, bit isMin,
                             MVEVectorVTInfo VTI, string intrBaseName,
                             ValueType Scalar, RegisterClass ScalarReg> {
   def "": MVE_VMINMAXNMV<iname, VTI.Suffix, VTI.Size{0}, notAbs, isMin>;
class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
   let Inst{17} = bit_17;
   let Inst{16} = 0b0;
   let Inst{15-12} = RdaDest{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+  let horizontalReduction = 1;
 }
 
 multiclass MVE_VMINMAXV_p<string iname, bit notAbs, bit isMin,
                           MVEVectorVTInfo VTI, string intrBaseName> {
   def "": MVE_VMINMAXV<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
                        notAbs, isMin>;
   defvar Inst        = !cast<Instruction>(NAME);
   defvar unpred_intr = !cast<Intrinsic>(intrBaseName);
class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
   let Inst{16} = sz;
   let Inst{15-13} = RdaDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
+  let horizontalReduction = 1;
 }
 
 multiclass MVE_VMLAMLSDAV_A<string iname, string x, MVEVectorVTInfo VTI,
                             bit sz, bit bit_28, bit X, bit bit_8, bit bit_0> {
   def ""#x#VTI.Suffix : MVE_VMLAMLSDAV<iname # x, VTI.Suffix,
                                    (ins MQPR:$Qn, MQPR:$Qm), "",
                                    sz, bit_28, 0b0, X, bit_8, bit_0>;
   def "a"#x#VTI.Suffix : MVE_VMLAMLSDAV<iname # "a" # x, VTI.Suffix,
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
   let Inst{16} = sz;
   let Inst{15-13} = RdaLoDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
+  let horizontalReduction = 1;
 }
 
 multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
                                bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
                                list<dag> pattern=[]> {
   def ""#x#suffix : MVE_VMLALDAVBase<
      iname # x, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
      sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;

llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

enum {
 
     // Whether an instruction can be included in an MVE tail-predicated loop.
     ValidForTailPredication = 1 << 20,
 
     // Whether an instruction writes to the top/bottom half of a vector element
     // and leaves the other half untouched.
     RetainsPreviousHalfElement = 1 << 21,
 
+    // Whether the instruction produces a scalar result from vector operands.
+    HorizontalReduction = 1 << 22,
+
     //===------------------------------------------------------------------===//
     // Code domain.
     DomainShift   = 15,
     DomainMask    = 15 << DomainShift,
     DomainGeneral = 0 << DomainShift,
     DomainVFP     = 1 << DomainShift,
     DomainNEON    = 2 << DomainShift,
     DomainNEONA8  = 4 << DomainShift,

llvm/unittests/Target/ARM/MachineInstrTest.cpp

 #include "ARMBaseInstrInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
+TEST(MachineInstructionHorizontalReduction, IsCorrect) {
+  using namespace ARM;
+
+  auto HorizontalReduction = [](unsigned Opcode) {
+    switch (Opcode) {
+    default:
+      break;
+    case MVE_VABAVs16:
+    case MVE_VABAVs32:
+    case MVE_VABAVs8:
+    case MVE_VABAVu16:
+    case MVE_VABAVu32:
+    case MVE_VABAVu8:
+    case MVE_VADDLVs32acc:
+    case MVE_VADDLVs32no_acc:
+    case MVE_VADDLVu32acc:
+    case MVE_VADDLVu32no_acc:
+    case MVE_VADDVs16acc:
+    case MVE_VADDVs16no_acc:
+    case MVE_VADDVs32acc:
+    case MVE_VADDVs32no_acc:
+    case MVE_VADDVs8acc:
+    case MVE_VADDVs8no_acc:
+    case MVE_VADDVu16acc:
+    case MVE_VADDVu16no_acc:
+    case MVE_VADDVu32acc:
+    case MVE_VADDVu32no_acc:
+    case MVE_VADDVu8acc:
+    case MVE_VADDVu8no_acc:
+    case MVE_VMAXAVs16:
+    case MVE_VMAXAVs32:
+    case MVE_VMAXAVs8:
+    case MVE_VMAXNMAVf16:
+    case MVE_VMAXNMAVf32:
+    case MVE_VMAXNMVf16:
+    case MVE_VMAXNMVf32:
+    case MVE_VMAXVs16:
+    case MVE_VMAXVs32:
+    case MVE_VMAXVs8:
+    case MVE_VMAXVu16:
+    case MVE_VMAXVu32:
+    case MVE_VMAXVu8:
+    case MVE_VMINAVs16:
+    case MVE_VMINAVs32:
+    case MVE_VMINAVs8:
+    case MVE_VMINNMAVf16:
+    case MVE_VMINNMAVf32:
+    case MVE_VMINNMVf16:
+    case MVE_VMINNMVf32:
+    case MVE_VMINVs16:
+    case MVE_VMINVs32:
+    case MVE_VMINVs8:
+    case MVE_VMINVu16:
+    case MVE_VMINVu32:
+    case MVE_VMINVu8:
+    case MVE_VMLADAVas16:
+    case MVE_VMLADAVas32:
+    case MVE_VMLADAVas8:
+    case MVE_VMLADAVau16:
+    case MVE_VMLADAVau32:
+    case MVE_VMLADAVau8:
+    case MVE_VMLADAVaxs16:
+    case MVE_VMLADAVaxs32:
+    case MVE_VMLADAVaxs8:
+    case MVE_VMLADAVs16:
+    case MVE_VMLADAVs32:
+    case MVE_VMLADAVs8:
+    case MVE_VMLADAVu16:
+    case MVE_VMLADAVu32:
+    case MVE_VMLADAVu8:
+    case MVE_VMLADAVxs16:
+    case MVE_VMLADAVxs32:
+    case MVE_VMLADAVxs8:
+    case MVE_VMLALDAVas16:
+    case MVE_VMLALDAVas32:
+    case MVE_VMLALDAVau16:
+    case MVE_VMLALDAVau32:
+    case MVE_VMLALDAVaxs16:
+    case MVE_VMLALDAVaxs32:
+    case MVE_VMLALDAVs16:
+    case MVE_VMLALDAVs32:
+    case MVE_VMLALDAVu16:
+    case MVE_VMLALDAVu32:
+    case MVE_VMLALDAVxs16:
+    case MVE_VMLALDAVxs32:
+    case MVE_VMLSDAVas16:
+    case MVE_VMLSDAVas32:
+    case MVE_VMLSDAVas8:
+    case MVE_VMLSDAVaxs16:
+    case MVE_VMLSDAVaxs32:
+    case MVE_VMLSDAVaxs8:
+    case MVE_VMLSDAVs16:
+    case MVE_VMLSDAVs32:
+    case MVE_VMLSDAVs8:
+    case MVE_VMLSDAVxs16:
+    case MVE_VMLSDAVxs32:
+    case MVE_VMLSDAVxs8:
+    case MVE_VMLSLDAVas16:
+    case MVE_VMLSLDAVas32:
+    case MVE_VMLSLDAVaxs16:
+    case MVE_VMLSLDAVaxs32:
+    case MVE_VMLSLDAVs16:
+    case MVE_VMLSLDAVs32:
+    case MVE_VMLSLDAVxs16:
+    case MVE_VMLSLDAVxs32:
+    case MVE_VRMLALDAVHas32:
+    case MVE_VRMLALDAVHau32:
+    case MVE_VRMLALDAVHaxs32:
+    case MVE_VRMLALDAVHs32:
+    case MVE_VRMLALDAVHu32:
+    case MVE_VRMLALDAVHxs32:
+    case MVE_VRMLSLDAVHas32:
+    case MVE_VRMLSLDAVHaxs32:
+    case MVE_VRMLSLDAVHs32:
+    case MVE_VRMLSLDAVHxs32:
+      return true;
+    }
+    return false;
+  };
+
+  LLVMInitializeARMTargetInfo();
+  LLVMInitializeARMTarget();
+  LLVMInitializeARMTargetMC();
+
+  auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
+  std::string Error;
+  const Target *T = TargetRegistry::lookupTarget(TT, Error);
+  if (!T) {
+    dbgs() << Error;
+    return;
+  }
+
+  TargetOptions Options;
+  auto TM = std::unique_ptr<LLVMTargetMachine>(
+    static_cast<LLVMTargetMachine*>(
+      T->createTargetMachine(TT, "generic", "", Options, None, None,
+                             CodeGenOpt::Default)));
+  ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+                  std::string(TM->getTargetFeatureString()),
+                  *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
+  const ARMBaseInstrInfo *TII = ST.getInstrInfo();
+  auto MII = TM->getMCInstrInfo();
+
+  for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
+    const MCInstrDesc &Desc = TII->get(i);
+
+    uint64_t Flags = Desc.TSFlags;
+    if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+      continue;
+
+    bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
+    ASSERT_EQ(HorizontalReduction(i), Valid)
+              << MII->getName(i)
+              << ": mismatched expectation for tail-predicated safety\n";
+  }
+}
+
 TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
   using namespace ARM;
 
   auto RetainsPreviousHalfElement = [](unsigned Opcode) {
     switch (Opcode) {
     default:
       break;
     case MVE_VMOVNi16bh: