[PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32

[jhibbits]

Summary

The linker is free to relax this (relocation R_PPC_GOT_TPREL16) against
R_PPC_TLS, if it sees fit (initial exec to local exec). If r0 is used,
this can generate execution-invalid code (converts to 'addi %rX, %r0,
FOO, which translates in PPC-lingo to li %rX, FOO). Forbid this
instead.

This fixes static binaries using locales on FreeBSD/powerpc
(tested on FreeBSD/powerpcspe).

[nemanjai]

Ah, OK. This makes sense.
I realize that it is not really possible to write a test case to show the allocation of R0 previous to this patch. However, would you modify existing test cases that use regex matching for the target register such as [[REG:[0-9]+]] to something like [[REG:[1-9][0-9]*]] to demonstrate that R0 is not a valid candidate for the regex match?

[jhibbits]

Update tests. Updated other tests in the same file that looked suspect as well.

[nemanjai]

LGTM. Thanks.

[MaskRay]

Thanks for this change. For PPC32 this helps GNU ld, gold and lld. The TLS Initial-Exec code sequence consists of 2 instructions.

For PPC64, the code sequence consists of 3 instructions. GNU ld and gold seem to special case r0 and use nop; nop; addi 0, 13, -28668 to avoid the issue.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 
 // Support for thread-local storage.
 def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
                          "#ADDISgotTprelHA",
                          [(set i64:$rD,
                            (PPCaddisGotTprelHA i64:$reg,
                                                tglobaltlsaddr:$disp))]>,
                   isPPC64;
-def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
+def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc_nox0:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
                         "#LDgotTprelL",
                         [(set i64:$rD,
                           (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
                  isPPC64;
 
 let Defs = [CR7], Itinerary = IIC_LdStSync in
 def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
 

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
                 [(set i32:$rD, (PPCppc32GOT))]>;
 
 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
 // This uses two output registers, the first as the real output, the second as a
 // temporary register, used internally in code generation.
 def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 
                 []>, NoEncode<"$rT">;
 
-def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
+def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
                            "#LDgotTprelL32",
                            [(set i32:$rD,
                              (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
           (ADD4TLS $in, tglobaltlsaddr:$g)>;
 
 def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
                          "#ADDItlsgdL32",

llvm/test/CodeGen/PowerPC/tls.ll

 ; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -O0 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
 ; RUN: llc -relocation-model=static -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -O1 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
 ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32-PIC %s
 
 @a = thread_local global i32 0, align 4
 
 ;OPT0-LABEL:          localexec:
 ;OPT1-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
-;OPT0:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
-;OPT0-NEXT:     addi [[REG2:[0-9]+]], [[REG1]], a@tprel@l
+;OPT0:          addis [[REG1:[1-9][0-9]*]], 13, a@tprel@ha
+;OPT0-NEXT:     addi [[REG2:[1-9][0-9]*]], [[REG1]], a@tprel@l
 ;OPT0-NEXT:     li [[REG3:[0-9]+]], 42
 ;OPT0:          stw [[REG3]], 0([[REG2]])
-;OPT1:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
+;OPT1:          addis [[REG1:[1-9][0-9]*]], 13, a@tprel@ha
 ;OPT1-NEXT:     li [[REG3:[0-9]+]], 42
 ;OPT1:     stw [[REG3]], a@tprel@l([[REG1]])
   store i32 42, i32* @a, align 4
   ret i32 0
 }
 
 ; Test correct assembly code generation for thread-local storage
 ; using the initial-exec model.
 
 @a2 = external thread_local(initialexec) global i32
 
 define signext i32 @main2() nounwind {
 entry:
   %retval = alloca i32, align 4
   store i32 0, i32* %retval
   %0 = load i32, i32* @a2, align 4
   ret i32 %0
 }
 
 ; OPT1-LABEL: main2:
-; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha
+; OPT1: addis [[REG1:[1-9][0-9]*]], 2, a2@got@tprel@ha
 ; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
 ; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls
 
 ;OPT0-PPC32-LABEL:    main2:
-;OPT0-PPC32:       li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l
+;OPT0-PPC32:       li [[REG1:[1-9][0-9]*]], _GLOBAL_OFFSET_TABLE_@l
 ;OPT0-PPC32:       addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@ha
-;OPT0-PPC32:       lwz [[REG2:[0-9]+]], a2@got@tprel([[REG1]])
+;OPT0-PPC32:       lwz [[REG2:[1-9][0-9]*]], a2@got@tprel([[REG1]])
 ;OPT0-PPC32:       add 3, [[REG2]], a2@tls
 
 ;OPT0-PPC32-PIC-LABEL:  main2:
 ;OPT0-PPC32-PIC:        .long _GLOBAL_OFFSET_TABLE_-{{.*}}
 ;OPT0-PPC32-PIC-NOT:    li {{[0-9]+}}, _GLOBAL_OFFSET_TABLE_@l
-;OPT0-PPC32-PIC-NOT:    addis {{[0-9]+}}, {{[0-9+]}}, _GLOBAL_OFFSET_TABLE_@ha
+;OPT0-PPC32-PIC-NOT:    addis {{[0-9]+}}, {{[1-9][0-9*]}}, _GLOBAL_OFFSET_TABLE_@ha
 ;OPT0-PPC32-PIC-NOT:    bl __tls_get_addr(a2@tlsgd)@PLT
-;OPT0-PPC32-PIC:        lwz {{[0-9]+}}, a2@got@tprel({{[0-9]+}})
+;OPT0-PPC32-PIC:        lwz {{[0-9]+}}, a2@got@tprel({{[1-9][0-9]*}})